No manufacturer publishes how many AI accelerators it has shipped, and no regulator collects the figure. Every unit count you have seen is a division problem with at least two uncertain inputs. This page runs the division and shows how much the answer moves.
Nobody publishes the number
What is published is revenue. NVIDIA reports a Data Center segment figure every quarter in its filings with the US Securities and Exchange Commission, and its competitors report their own equivalents. Revenue is audited and unambiguous. Units are neither published nor derivable without assumptions, for three reasons that compound.
- The segment is not only chips. Data Center revenue includes networking, whole systems, and in some cases software and services. The fraction that is accelerator silicon is not disclosed separately in a way that supports division.
- There is no single product. Several generations and several memory configurations ship simultaneously at very different prices, and the mix changes every quarter.
- Prices are negotiated. A hyperscaler buying at enormous volume does not pay the price a rumoured list quotes, and the discount is confidential.
Route one: revenue divided by price
The arithmetic is trivial. The difficulty is entirely in the inputs, so write it as algebra first and only then put numbers in.
units = (R * f) / P
R = reported segment revenue for the period
f = fraction of that revenue attributable to accelerator silicon
P = average realised selling price per accelerator
Illustrative arithmetic, not a claim about any actual quarter.
Take R = $30 billion for one quarter, and bracket the two unknowns:
f in [0.70, 0.90] accelerators as a share of segment revenue
P in [$20k, $35k] average realised price per unit
low estimate: 30e9 * 0.70 / 35,000 = 600,000 units
high estimate: 30e9 * 0.90 / 20,000 = 1,350,000 units
Six hundred thousand to one and a third million, from the same revenue figure. The spread is a factor of 2.25 and it comes entirely from two assumptions neither of which anyone outside the companies can pin down.
How wide the error bars are
The reason to write it as (R * f) / P rather than as a single number is that you can then see how each input propagates. Because the expression is a product and a quotient, relative errors multiply rather than add.
For units = (R * f) / P, relative uncertainties combine as:
(du/u)^2 ~= (dR/R)^2 + (df/f)^2 + (dP/P)^2
With R known exactly (dR/R = 0) and each of the other two uncertain to
plus or minus 20%:
du/u = sqrt(0 + 0.20^2 + 0.20^2) = 0.283
So even a "careful" estimate carries about plus or minus 28% before you
have accounted for mix changes, channel inventory or the difference
between shipped and installed.
Anyone quoting a unit count to three significant figures is quoting
noise. Round to the nearest order of magnitude, or to one significant
figure at most.
This is the discipline that most published chip-count estimates skip, and it is the reason two reputable analysts can differ by a factor of two without either being wrong.
Route two: the memory supply chain
A better-constrained route runs through high-bandwidth memory. Every modern accelerator carries a known quantity of HBM, and HBM is made by only three companies — SK hynix, Samsung and Micron — all of which are publicly listed and discuss HBM capacity in their quarterly results.
units = total_HBM_shipped_GB / HBM_per_accelerator_GB
Manufacturer specifications give the denominator precisely. For example
NVIDIA's published specifications put the H100 SXM at 80 GB of HBM3 and
the H200 at 141 GB of HBM3e.
10 million GB of HBM / 80 GB per unit = 125,000 units
10 million GB of HBM / 141 GB per unit = 71,000 units
Same memory, different generation, nearly a factor of two in units.
The advantage of this route is that the denominator is a published hardware specification rather than a negotiated price. The disadvantage is that the numerator is reported in revenue and bit growth rather than in gigabytes, so you are back to a conversion.
The related and frequently more binding constraint is advanced packaging: the interposer technology that attaches HBM stacks to the logic die. TSMC discusses its packaging capacity on its quarterly earnings calls, and that capacity, rather than wafer starts, has been the stated bottleneck. If you want one number to watch as a proxy for accelerator supply, packaging capacity is a better one than wafer output. There is more on the hardware constraints in the GPU shortage page.
Route three: the power envelope
A third route bounds the fleet from the electricity it consumes, and it is useful because grid connections and data-centre power are reported by utilities and regulators in many jurisdictions.
units ~= (IT_power_MW * 1e6) / power_per_accelerator_W
Take a data-centre campus with 100 MW of IT load, and assume the
accelerator itself accounts for roughly half of IT power once you
include CPUs, networking, storage and losses inside the rack:
accelerator power = 50 MW = 5.0e7 W
at 700 W per accelerator -> 71,000 accelerators
at 1,000 W per accelerator -> 50,000 accelerators
The 700 W figure is the published TDP class of current top-end
data-centre parts; check the datasheet for the specific part.
This route bounds rather than counts, but bounds are valuable: it tells you immediately that a claim of millions of frontier accelerators in one facility is not a claim about hardware, it is a claim about gigawatts. The energy side is covered in data-centre energy use.
Shipped is not running
Even a perfect unit count would not answer the question people mean. Four gaps sit between chips shipped and compute available.
| Gap | Description |
|---|---|
| in transit | Shipped in a quarter, powered on months later. Data-centre construction and grid connection are the long poles, not the silicon. |
| retired | Older generations are still counted in cumulative shipments long after they stop being economic to run. Cumulative shipments over-state the fleet. |
| not fungible | An accelerator with 40 GB of memory cannot serve a model that needs 140 GB, however many of them you have. Counting units ignores whether they can run the workload — see the VRAM arithmetic in the model file size page. |
| idle | Utilisation is not 100%. Fleets are sized for peak, and reservation does not mean use. |
What to cite instead
If you need a defensible statement about AI hardware supply, cite a quantity that is actually reported rather than one that is derived.
- Segment revenue from the filing. NVIDIA’s 10-Q and 10-K, and the equivalent filings from AMD, Broadcom and the hyperscalers. Audited, dated, and available free from the SEC’s EDGAR database.
- Capital expenditure from cash flow statements. What the buyers spent, which is a cleaner signal than what anyone thinks they bought. See what the big labs spend.
- Memory and packaging commentary from the earnings calls of the three HBM makers and TSMC. Transcripts are public.
- Announced data-centre capacity in megawatts, from company announcements and utility interconnection queues. Power is harder to exaggerate than chips because somebody has to build the substation.
- Export-control filings and thresholds, which define categories of accelerator in terms of measurable performance characteristics and are published in the register. See export controls.
Every figure in this area moves quarterly and the product mix changes faster than the revenue does. Treat any unit count, including one you derive with the arithmetic above, as valid for the quarter it was computed for and for no other.
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