I Built a Hardware Description Language with JUST logic gates (and Here’s Why)

#programming #python #c #opensource

Most hardware description languages try to make hardware design easier by adding abstraction: arithmetic operators, inferred widths, behavioral blocks, and synthesis-friendly constructs.

SHDL takes the opposite approach.

I built SHDL (Simple Hardware Description Language) as an experiment in radical minimalism: what happens if you describe hardware using nothing but logic gates, wires, and explicit connections?

There are no adders, no “+”, no implicit registers. If you want a full adder, you build it from XOR, AND, and OR gates. If you want a CPU, you compose it from those adders, registers, multiplexers, and control logic—manually.

Why do this?

Because abstraction hides understanding.

Modern HDLs are incredibly powerful, but they also make it easy to forget what hardware is. SHDL is designed to force the designer to confront the physical reality of digital logic: signals, propagation, composition, and structure.

What SHDL is (and isn’t)

SHDL is:

an educational and experimental HDL
a way to learn digital logic from first principles
a playground for language and tooling design

SHDL is not:

a replacement for Verilog or VHDL
optimized for synthesis or production hardware
focused on convenience

To make experimentation practical, I built PySHDL, a Python interface that lets you simulate SHDL circuits programmatically. You can load a circuit, set inputs, step the clock, and inspect outputs directly from Python, which makes it easy to write tests or interactive experiments.

Internally, SHDL compiles circuits to C for execution, but the language itself stays deliberately small and explicit.

What I’m looking for

This project is still evolving, and I’m very interested in feedback from: