Introducing the Reusable Verification Platform (RVP) from WIOWIZ, designed to expedite the chip Design verification process. RVP generates the environment and simulates it on FSiMX, our proprietary functional simulator, eliminating the need for any third-party dependencies throughout the verification chain.
YAML in → UVM environment out → compiled, elaborated, simulated → coverage reported. The entire flow is WIOWIZ, end to end.
Key features include:
- Describe your SoC's bus architecture (APB, AHB-Lite, AXI4) and peripherals (UART, SPI, I2C, CAN FD, Timer, PWM, ADC, DMA, etc.), and RVP generates a complete testbench.
Environment that includes:
- Per-IP agents with driver, monitor, and sequencer
- Protocol-specific VIP checkers and coverage collectors
- Auto-generated functional coverpoints, cross-coverage bins, and SVA assertions per IP
- A comprehensive coverage plan for review before simulation begins
We are sharing this in beta to address the verification infrastructure challenge, the extensive time spent wiring environments before the first real test.
The free tier allows you to build a simple microcontroller-class SoC, view the complete generated architecture, review the coverage plan, and run simulations. Templates and UVM structure are visible, and full VIP source is licensed. ( Soon we will add complete test suite )
The methodology focuses on functional coverage-driven tests to ensure code coverage, with every test created to meet a coverage bin requirement.
Please share your feedback on what’s missing.
Our roadmap extends to ADAS, SensorFusion, DPU, TCON/DDI, and application processor-class SoCs featuring high-speed interfaces and memory subsystems.
WIOWIZ Technologies | FSiMX Cloud v0.6.0 Beta
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