Why Impedance Control Defines Modern PCB Design
Every signal above a few hundred megahertz behaves as a transmission line. When the signal's rise time creates wavelengths comparable to the trace length, controlled impedance stops being optional and becomes the single most important aspect of your PCB stackup design.
Get impedance wrong → reflections, ringing, eye diagram degradation, bit errors. Get it right → your 56 Gbps PAM4 channels work on the first spin.
What Determines Impedance?
Characteristic impedance (Z₀) depends on four properties:
- Trace width (W) — wider = lower impedance
- Dielectric thickness (H) — thicker = higher impedance
- Dielectric constant (Dk/εr) — higher Dk = lower impedance
- Copper thickness (T) — thicker copper slightly reduces impedance
The relationship:
Z₀ ∝ √(L/C) ∝ (H/W) × (1/√Dk)
Impedance is fundamentally a ratio of height-to-width scaled by dielectric properties.
Microstrip vs. Stripline: When to Use Each
| Property | Microstrip | Stripline |
|---|---|---|
| Location | Outer layers | Inner layers |
| Reference planes | One (below) | Two (above + below) |
| Impedance formula | More complex (air/dielectric interface) | Simpler (uniform dielectric) |
| Typical 50Ω width | 7-8 mil (4 mil prepreg, Dk 4.2) | 4-5 mil (symmetric, Dk 4.2) |
| Radiation/crosstalk | Higher (exposed to air) | Lower (shielded by planes) |
| Best for | Short runs, component connections | Long interconnects, sensitive signals |
Rule of thumb: Use stripline for any trace longer than λ/10 at the signal's knee frequency. Use microstrip for short breakout routing from components.
Standard Impedance Targets by Interface
| Interface | Single-ended (Ω) | Differential (Ω) | Speed |
|---|---|---|---|
| USB 2.0 | — | 90 ±10% | 480 Mbps |
| USB 3.x/4 | — | 85 ±10% | 5-40 Gbps |
| PCIe Gen 3-5 | — | 85 ±10% | 8-32 GT/s |
| PCIe Gen 6 | — | 85 ±5% | 64 GT/s |
| DDR4 | 40 ±10% | 80 ±10% | 3.2 GT/s |
| DDR5 | 40 ±10% | 80 ±10% | 4.8-6.4 GT/s |
| 100G Ethernet | — | 100 ±10% | 25G/lane |
| HDMI 2.1 | — | 100 ±10% | 12 Gbps |
Manufacturing Tolerances: What Your Fab Can Actually Hold
Standard vs. Tight Tolerance
| Parameter | Standard | Tight | Impact on impedance |
|---|---|---|---|
| Dielectric height | ±0.5 mil | ±0.25 mil | ±5-8% |
| Trace width (etch) | ±0.5 mil | ±0.3 mil | ±3-6% |
| Dk variation | ±5% | ±2% | ±2-3% |
| Copper thickness | ±10% | ±5% | ±1-2% |
| Combined worst-case | ±10-15% | ±5-8% | — |
This is why ±10% impedance tolerance is the industry standard — it's the natural outcome of standard manufacturing processes. Achieving ±5% requires premium materials, tighter process control, and additional cost.
Cost Impact of Tighter Tolerances
- ±10% tolerance: Standard pricing (no adder)
- ±7% tolerance: 10-15% cost premium
- ±5% tolerance: 15-25% cost premium + TDR testing
- ±3% tolerance: 30-50% premium + material selection + individual panel testing
Material Selection by Data Rate
| Data Rate | Material Class | Examples | Dk @ 10 GHz | Df @ 10 GHz |
|---|---|---|---|---|
| < 5 Gbps | Standard FR-4 | Shengyi S1000-2 | 4.2-4.5 | 0.018-0.022 |
| 5-16 Gbps | Mid-loss | IT-180A, 370HR | 3.9-4.2 | 0.010-0.015 |
| 16-56 Gbps | Low-loss | Megtron 4, Tachyon | 3.7-4.0 | 0.005-0.008 |
| 56-112 Gbps | Ultra-low-loss | Megtron 7, Tachyon-100G | 3.4-3.7 | 0.002-0.004 |
| RF (>1 GHz) | RF-grade | Rogers RO4350B | 3.48 | 0.0037 |
Critical insight: Standard FR-4 Dk varies by 5-10% between lots and across frequency. Low-loss materials hold Dk within ±2% — this directly improves impedance consistency without changing manufacturing tolerance.
Practical Stackup Design Workflow
Step 1: Define Impedance Requirements
List every controlled impedance net class with target value and tolerance.
Step 2: Choose Material System
Based on data rate requirements (see table above).
Step 3: Initial Geometry Calculation
Use a field solver (Polar SI9000, Saturn PCB, or your EDA tool's built-in solver):
- Input: target impedance, available dielectric thickness, copper weight
- Output: required trace width
Step 4: Verify Against Manufacturing Constraints
- Is the trace width achievable? (≥ 3 mil for standard, ≥ 3.5 mil with margin)
- Is the dielectric thickness available from your material supplier?
- Does the geometry fit your routing density requirements?
Step 5: Send Stackup to Fabricator for Review
Before routing. Your fabricator will:
- Confirm material availability
- Adjust dielectric thicknesses to match actual prepreg/core stock
- Run their own impedance simulation
- Identify any issues with your assumed Dk values
Common Mistakes That Kill Impedance
1. Using Datasheet Dk Instead of Process Dk
Rogers RO4350B is Dk 3.48 on the datasheet. In your actual stackup with prepreg bonding, resin flow, and copper roughness effects, the effective Dk might be 3.55-3.65. Always use your fabricator's process-adjusted Dk values.
2. Ignoring Soldermask Effect on Microstrip
Soldermask (Dk ~3.5-4.0) covering outer-layer traces changes microstrip impedance by 2-5 Ω. Your field solver must model the soldermask layer.
3. Reference Plane Breaks
A trace crossing a split in its reference plane sees a sudden impedance discontinuity. Route signals parallel to splits, never across them.
4. Via Transitions Without Stitching
Every via transition needs a nearby ground via to maintain the return current path. Missing ground stitching causes 10-20 Ω impedance spikes at via locations.
5. Assuming Symmetric Stripline When It Isn't
If your trace is offset between two reference planes (asymmetric stripline), the impedance calculation differs significantly from symmetric. Check your actual stackup geometry.
TDR Verification: What to Expect
Time Domain Reflectometry (TDR) measures actual impedance along a trace:
- Test coupon: Dedicated impedance test structures on panel border
- Resolution: ~1mm spatial resolution with modern TDR equipment
- Report: Shows impedance profile along coupon length
- Pass criteria: All points within specified tolerance band
What TDR Cannot Tell You:
- Impedance of actual product traces (only coupon)
- Dk/Df values (derived measurement, not direct)
- Whether your design will work at speed (impedance is necessary but not sufficient)
Quick Reference: 50Ω Trace Widths
For common stackup configurations (FR-4, Dk 4.2, 1 oz copper):
| Configuration | Dielectric | 50Ω Width |
|---|---|---|
| Outer microstrip | 3 mil prepreg | 5.5 mil |
| Outer microstrip | 4 mil prepreg | 7.5 mil |
| Outer microstrip | 5 mil prepreg | 9.5 mil |
| Inner stripline (symmetric) | 4+4 mil | 4.5 mil |
| Inner stripline (symmetric) | 5+5 mil | 5.5 mil |
| Inner stripline (symmetric) | 8+8 mil | 9 mil |
These are estimates. Always verify with a field solver using your actual material properties.
Key Takeaways
- Impedance is a ratio — H/W × 1/√Dk. Understanding this makes stackup design intuitive.
- ±10% is standard, ±5% costs more. Choose based on your interface requirements.
- Material matters more than geometry for consistency — stable Dk = stable impedance.
- Talk to your fabricator before routing — they know what dielectric thicknesses are actually available.
- Use field solvers, not formulas — the simplified equations are only accurate within ±15%.
- TDR verifies manufacturing, not design — it confirms the fabricator hit the target.
Originally published at AtlasPCB Engineering Blog. We provide impedance-controlled PCB fabrication with ±5% tolerance, TDR-verified on every panel, for high-speed digital and RF applications.
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