The single most common reason impedance-controlled PCBs fail incoming inspection is not a manufacturing defect — it is an incomplete or ambiguous specification. In DFM review, impedance issues get flagged on roughly 35% of new customer designs, and the overwhelming majority are specification gaps rather than design errors.
Impedance Specification Checklist
Before submitting your design to any PCB manufacturer, verify these items exist in your fab drawing:
| Required Information | Example |
|---|---|
| Target impedance (single-ended) | 50 ohm +/-10% |
| Target impedance (differential) | 100 ohm +/-10% |
| Reference layer(s) | L2 ground plane |
| Trace width (calculated) | 4.5 mil |
| Differential pair spacing | 5.0 mil gap |
| Dielectric material | FR-4 Tg170 |
| Dielectric thickness | 4.5 mil prepreg |
| Dk value assumed | 4.2 @ 1 GHz |
| TDR coupon requirement | Yes, per panel |
Why Specs Get Lost Between Design and Fabrication
Your EDA tool (Altium, Cadence, KiCad) calculates trace widths based on idealized dielectric properties and stackup assumptions. The actual material your manufacturer stocks may have slightly different Dk values, different prepreg thicknesses after pressing, and different copper roughness profiles.
Without clear communication of your assumptions, the manufacturer cannot verify whether their actual materials will meet your impedance targets. This creates the "gap" that causes first-article failures.
Step 1: Define Your Impedance Classes
Organize your impedance requirements into classes. Designs with clearly labeled impedance classes have 3x fewer DFM questions during review:
Class A: Single-ended 50 ohm +/-10% — General high-speed signals. Microstrip on L1/L8 referenced to adjacent ground. Trace width: 4.5 mil.
Class B: Differential 100 ohm +/-10% — DDR4 data pairs. Stripline on L3. Trace: 3.8 mil, gap: 5.0 mil.
Class C: Differential 85 ohm +/-7% — PCIe Gen4 lanes. Stripline on L4. Tighter tolerance for 16 GT/s signaling.
Class D: Single-ended 50 ohm +/-5% — RF signal (2.4 GHz). Microstrip on Rogers RO4350B.
Step 2: The Stackup Table
Your stackup table is the most critical document for impedance control. For each layer, include:
- Layer number and function
- Copper weight (finished)
- Dielectric material and thickness
- Expected Dk at operating frequency
- Impedance target for signal layers
- Reference plane designation
Critical notes to include below:
- "Manufacturer may adjust trace width +/-0.5 mil to achieve target impedance"
- "Prepreg thickness is post-lamination target"
- "Dk values from simulation are at 1 GHz — use frequency-dependent Dk if available"
Step 3: Common Mistakes That Cause Failures
Based on thousands of impedance-controlled DFM reviews:
Mistake 1: No reference layer specified. "50 ohm on L1" without stating whether L2 is ground or power. If L2 has splits under your traces, impedance will be significantly higher.
Mistake 2: Using EDA default Dk values. Altium defaults to Dk=4.5 for FR-4. If the manufacturer uses Isola 370HR (Dk=3.92), your calculated trace width produces incorrect impedance.
Mistake 3: No differential pair geometry specified. "100 ohm differential" is insufficient. The manufacturer needs: edge-coupled or broadside? What gap? Does spacing change at breakout?
Mistake 4: Ignoring copper roughness above 5 GHz. Standard oxide treatment adds 3-5 um roughness. At 10+ GHz, this shifts impedance 2-5%.
Mistake 5: Over-specifying tolerance. +/-5% requires tighter controls and adds 15-30% cost. Most DDR4 works fine at +/-10%. Only PCIe Gen5 genuinely needs +/-7%.
Step 4: TDR Verification
TDR (Time Domain Reflectometry) coupon measurement is the gold standard for impedance verification. Request it when:
- Impedance is functionally critical
- Medical, aerospace, or automotive applications (IPC-6012 Class 3)
- Tolerance is +/-7% or tighter
- First article inspection on new designs
- Qualifying a new manufacturer
Specify in your fab notes:
- TDR measurement on every production panel
- Coupons replicating actual trace geometry
- Pass/fail criteria matching your tolerance band
- Minimum 2 coupons per impedance class per panel
Step 5: Collaborative Specification Process
Before layout: Get your manufacturer's actual material Dk values. Design trace widths using their data, not textbook values.
During DFM: Expect adjustments. A 0.2 mil trace width change for actual Dk is normal. What matters is communication before production.
After first article: Review TDR reports critically. If measured impedance rides the edge of tolerance, discuss adjustment for subsequent lots.
The Complete Package
Your impedance documentation should contain:
- Fab drawing with impedance table (target Z, tolerance, reference, class)
- Stackup with material, Dk, and dielectric thickness per layer
- Authorization for trace width adjustment within limits
- TDR verification requirement and acceptance criteria
Getting this right eliminates the primary source of failures and saves weeks of respin time.
Originally published at AtlasPCB Engineering Blog. We provide field-solver verification and per-panel TDR testing on every impedance-controlled order.
Related: PCB Stackup Design Guide
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