Budget PCB fabs like JLCPCB skip backdrilling, leaving via stubs that destroy signal integrity above 5 Gbps. If your design runs any differential pair above 8 Gbps through a via transition in a board thicker than 1.6mm, you need a custom manufacturer with depth-controlled backdrilling.
The Problem: Via Stubs Are Killing Your High-Speed Channel
A through-hole via in a multilayer PCB creates a stub — the unused portion of the barrel extending beyond the target layer. In an 8-layer, 1.6mm board where a signal transitions from Layer 1 to Layer 3, the remaining stub from Layer 3 to Layer 8 is approximately 50 mils of unterminated transmission line.
This stub acts as a quarter-wave resonant cavity, creating a notch in your channel's frequency response at:
f_resonance = c / (4 × stub_length × √Dk)
For a typical 50-mil stub in FR-4 (Dk=4.0), the first resonance hits at approximately 15 GHz — right in the Nyquist frequency of a 25 Gbps NRZ signal.
Real Measurement Data
Consider a 10-layer, 2.0mm board with signal transitioning from Layer 1 to Layer 4:
| Parameter | Without Backdrilling | With Backdrilling |
|---|---|---|
| Stub length | 65 mil (L4→L10) | 8 mil residual |
| First stub resonance | 11.5 GHz | 94 GHz |
| IL at 12.5 GHz (25G Nyquist) | -4.2 dB | -0.3 dB |
| IL at 8 GHz (PCIe Gen5) | -2.1 dB | -0.1 dB |
| Eye height at 25 Gbps | Fail | Pass |
The difference isn't subtle — it's the difference between a compliant channel and a failed one.
What Budget Fabs Cannot Do
Backdrilling requires:
- CNC drilling machine with Z-axis depth control
- Separate drill program from layer assignment data
- Operator verification via cross-section microsectioning
- Drill bits 0.1-0.2mm larger than the original via
This is fundamentally incompatible with the high-volume, minimal-touch workflow that makes JLCPCB affordable. Their model depends on zero-touch automation — which is great for simple boards but breaks down for high-speed designs.
The Honest Decision Framework
JLCPCB is adequate when:
- Max data rate below 5 Gbps (USB 2.0, SPI, I2C, 1G Ethernet)
- Board thickness ≤ 1.0mm
- No via transitions on high-speed differential pairs
- Layer count ≤ 4 (limited stub length)
You need a custom manufacturer when:
- Any signal at 10+ Gbps (PCIe Gen 4/5, 25G/100G Ethernet, USB4)
- Board thickness > 1.6mm with through-hole vias on signal nets
- Design targets IEEE or PCI-SIG compliance
- Rise time below 100 ps through via transitions
The Real Cost Math
| Factor | JLCPCB (8L, 1.6mm) | Custom Fab + Backdrill |
|---|---|---|
| Board cost (5 pcs) | $45-80 | $180-350 |
| Backdrilling | Not available | Included |
| Impedance tolerance | ±10% | ±5% with TDR |
| DFM review | Automated only | Engineer review |
| Cost of SI failure respin | $5,000-15,000 | Avoided |
The per-board premium is 3-5x. But for high-speed designs, the total cost of ownership — including potential respins, compliance test failures, and schedule delays — heavily favors getting it right the first time.
We've seen companies spend $50,000+ debugging a signal integrity problem that a $300 backdrill operation would have prevented entirely.
Specification Tips for Your Fab Drawing
If you need backdrilling, specify:
- Which vias require backdrill (separate drill chart entry)
- Target layer for each backdrill group
- Maximum residual stub (recommend 8-10 mil)
- Backdrill diameter (0.1-0.2mm larger than original via)
Common mistakes:
- Requesting backdrilling on vias connecting multiple internal layers
- Specifying stub < 5 mil (below manufacturing capability)
- Forgetting backdrill entry pad on opposite side
Bottom Line
The PCB industry has a clear capability divide. Budget fabricators optimize for volume and price — they're excellent for designs within their process window. But high-speed designs operating above 5-10 Gbps need capabilities (backdrilling, tight impedance control, engineering DFM review) that simply don't exist in the budget tier.
Know which side of that line your design falls on before you place your order.
Originally published on AtlasPCB Engineering Blog. We manufacture impedance-controlled multilayer PCBs with backdrilling (±3 mil depth accuracy) for high-speed digital applications up to 30 layers.
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