Most engineers treat PCB pricing as a black box — upload Gerbers, get a number. But fabrication cost is fundamentally determined by which manufacturing processes your design requires. Every factory has a "standard" process window that handles the majority of orders at high yield and minimal setup. When your design falls outside that window, it triggers specialized equipment, slower processing, or additional quality gates that directly increase cost.
The 8 Rules That Keep Your PCB in Standard Pricing
| Rule | Standard (Low Cost) | Premium (High Cost) | Cost Impact |
|---|---|---|---|
| Min trace/space | 5/5 mil or wider | < 4/4 mil | +10-25% |
| Min drill size | 0.3mm or larger | < 0.2mm (laser) | +20-40% |
| Layer count | 2 or 4 layers | 8+ layers | +$3-8/layer pair |
| Board thickness | 1.6mm standard | Non-standard | +10-20% |
| Surface finish | HASL or OSP | ENIG | +30-60% |
| Impedance control | None specified | +/-5% controlled | +10-25% |
| Aspect ratio | < 8:1 | > 10:1 | +15-30% |
| Panel utilization | > 80% material use | < 60% material use | +15-40% |
Follow these thresholds and your board stays in standard fabrication processes. Cross any threshold and you enter premium pricing territory.
Rule 1: Trace Width and Spacing — The LDI Threshold
The single most impactful cost variable in PCB imaging is whether your design can be processed with conventional phototool (film) exposure or requires laser direct imaging (LDI). Conventional film exposure handles 4/4mil (100um) trace/space reliably at essentially no extra cost per panel. Once you drop below 4/4mil, most fabricators switch to LDI — a sequential, slower process that adds 10-25% to imaging cost per layer.
The sweet spot is 5/5mil for fine-pitch BGA escape routing and 6/6mil or wider everywhere else. If you only need tight trace/space in one small area around a BGA, some fabricators can use conventional imaging with a local tolerance note without charging LDI rates globally.
Ground and power planes never need tight trace/space. Set inner-layer ground planes to 8/8mil clearances and only apply 5/5mil rules on routing layers where you need density.
Rule 2: Drill Size — Mechanical vs Laser Breakpoint
PCB drilling is priced in tiers based on the smallest hole. Holes 0.3mm and larger are processed at full mechanical drill speed (150k-200k hits/spindle/hour). Between 0.2mm and 0.3mm, drill speed drops and bit breakage increases (+10-15% cost). Below 0.2mm triggers laser drilling — a fundamentally different process adding 20-40% to via processing cost.
The critical insight: if your design has even one via at 0.15mm while the rest are 0.3mm, the entire panel may need laser processing for that layer pair. Contain microvias to HDI buildup layers and keep core vias at 0.3mm or larger.
Another overlooked factor is drill aspect ratio. A 0.3mm hole through 1.6mm board = 5.3:1 ratio (standard). Same hole through 3.0mm = 10:1 (premium pricing). If your board is thick, size vias proportionally.
Rule 3: Layer Count — Each Pair Is a Press Cycle
Every additional pair of signal layers adds a lamination cycle: layup, vacuum press at 180C for 90+ minutes, cool-down, and inspection. Each cycle adds $3-8/board at prototype quantities, and yield risk compounds with each additional press cycle.
A surprisingly large number of 6-layer designs can route on 4 layers with slightly wider board dimensions or a few additional vias. Before committing to 6+ layers, try routing critical nets on 4 layers. If you achieve 85%+ route completion, the remaining nets can often be accommodated.
For HDI boards where you genuinely need 8+ layers with microvias, minimize sequential lamination cycles. A 2+N+2 buildup is typically 40-60% cheaper than a full any-layer structure with the same total layer count.
Rule 4: Material and Thickness Selection
Standard FR-4 at 1.6mm is the default for most fabricators. Deviating incurs surcharges:
- Non-standard thickness (0.4, 0.8, 2.0, 3.2mm): +10-20% material cost
- High-Tg FR-4 (Tg170+): +5-15% over standard Tg135-150
- Specialty laminates (Rogers, PTFE): 3-10x FR-4 material cost
Unless your board sees sustained temperatures above 130C in operation, standard-Tg material works. Many engineers reflexively specify High-Tg when their actual operating temperature never exceeds 85C.
If your design only needs specialty material for one or two RF signal layers, consider a hybrid stackup — Rogers for RF layers and FR-4 for the rest. This can cut material cost by 40-60% compared to all-Rogers construction.
Rule 5: Surface Finish Cost Hierarchy
Surface finish is the easiest cost lever because it has zero impact on routing, stackup, or layer count:
- HASL: baseline ($0)
- OSP: +5-8%
- Immersion Tin: +8-12%
- Immersion Silver: +15-25%
- ENIG: +30-60%
- Hard Gold (selective): +80-200%
For prototypes assembled within 30 days, HASL or OSP are perfectly adequate. ENIG is only justified for wire-bondability, ultra-fine-pitch BGAs (< 0.4mm), or boards stored 6+ months.
Rule 6: Panelization for Material Utilization
Fabricators process boards in standardized panel sizes (typically 18x24 inches). Your per-board price is heavily influenced by how efficiently boards fit the working panel.
Sometimes adding 2-3mm to one board dimension (costs nothing functionally) allows one more row per panel — reducing per-unit cost by 10-20%. For small boards (under 50x50mm), ordering as panelized arrays with V-score breakaway is 3-5x cheaper per piece than individual boards.
Rule 7: Avoid Accidental Premium Triggers
Common specs that trigger premium pricing unnecessarily:
- Controlled impedance when your fastest signal is I2C at 400 kHz
- Carbon ink printing for a test point that could use standard copper
- Edge plating when the board doesn't actually need it
- Peelable solder mask for one connector that could use selective wave soldering instead
- Gold fingers on a board that uses a standard header connector
Every special process is a setup cost. Only specify what your design genuinely requires.
Rule 8: The Cost-Optimization Checklist
Before submitting for quote, check each item:
- Can any trace/space be widened from 4/4mil to 5/5mil?
- Are all vias 0.3mm or larger?
- Is the layer count the absolute minimum for routing?
- Can you use standard 1.6mm FR-4 with Tg135-150?
- Does assembly really require ENIG, or will HASL/OSP work?
- Can impedance tolerance relax from +/-5% to +/-10%?
- Is board outline optimized for panel utilization?
- Have you specified only the special processes you actually need?
A design answering "yes" to all eight typically prices 30-50% lower than one specifying premium processes by default. The technical performance is often identical.
Designing for minimum cost? Upload your Gerber files and our system auto-detects cost drivers, showing exactly which specs add cost. Standard 5-18 day lead time with 1-day rush available. Get instant pricing.
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