The Problem: 34% of First-Time PCB Orders Have DFM Errors
Based on our production data from H1 2026, approximately one-third of new customer orders require at least one design revision before manufacturing can begin. Each revision cycle adds 1-3 days to delivery. This article covers the 12 most common DFM errors — ranked by frequency — with IPC standard references and fixes for your CAD tool.
The 12 Critical DFM Errors (Ranked by Frequency)
1. Annular Ring Violations (23% of rejections)
The annular ring is the copper pad remaining around a drilled hole after manufacturing tolerances. IPC-6012 Class 2 requires minimum 5mil (0.127mm). Class 3 (aerospace, medical) requires 5mil with no breakout.
The mistake happens when designers use via definitions from older libraries without verifying pad-to-drill relationships. A common failure: using a 0.3mm drill with a 0.5mm pad gives only 4mil annular ring per side — below minimum before accounting for drill registration tolerance (+/-2mil).
Fix: Minimum pad diameter = drill size + 10mil. For 0.3mm drills, use 0.55mm pads minimum. In Altium: Design Rules > Manufacturing > Minimum Annular Ring. In KiCad: set DRC to 0.125mm minimum.
2. Acid Traps and Acute Angles (18% of rejections)
Acute-angle trace junctions below 90 degrees create etching problems. The etchant becomes trapped in the sharp interior angle, over-etching the copper and potentially creating opens. This is particularly problematic at fine-pitch routing (3/3mil or 4/4mil).
Fix: Ensure all trace junctions are 90 degrees or greater. Use 45-degree routing rather than arbitrary angles. Run an acute angle check with threshold of 90 degrees.
3. Solder Mask Dam Violations (14% of rejections)
The mask dam between adjacent SMD pad openings must be at least 3mil (75um) for LPI solder mask. When this dam is too narrow, solder bridges during assembly.
For HDI PCBs with 0.4mm-pitch BGAs, expanding mask openings for better wetting without considering dam width is a common trap.
Fix: Minimum 3mil dam for standard LPI, 2mil for LDI processes. Check mask-to-mask clearance on all fine-pitch components.
4. Floating Copper and Unconnected Pours (11% of rejections)
Copper pour regions not connected to any net act as antennas and can detach during etching. Small isolated features may contaminate the etching line, causing defects on other panels.
Fix: After generating all copper pours, run DRC for unconnected copper. Remove islands smaller than 0.5mm square.
5. Trace-to-Edge Clearance (9% of rejections)
Board edge routing has mechanical tolerances. V-score has +/-4mil accuracy; tab routing +/-4-8mil. IPC-6012 requires minimum 10mil copper-to-edge for external layers, 15mil for internal.
Fix: 10mil minimum external, 15mil internal. If copper MUST reach the edge (ground for RF connectors), specify it explicitly in fab notes.
6. Drill-to-Copper Clearance (8% of rejections)
Non-plated holes must maintain 10mil clearance to copper on all layers. NPTHs without proper anti-pads on internal planes will drill through live copper.
Fix: Ensure NPTH holes have anti-pad definitions on ALL copper layers, not just external.
7. Impedance Stackup Infeasibility (7% of rejections)
Engineers specify impedance targets without verifying the stackup can achieve them with available prepreg thicknesses. Example: requesting 50 ohm microstrip with 3.5mil trace on 4mil dielectric — the required dielectric height is 5.2mil, matching no standard prepreg.
Fix: Use a 2D field solver (Polar Si9000, Saturn PCB Toolkit) to verify impedance targets against actual prepreg thicknesses. Request a stackup proposal from your manufacturer before routing.
8. Missing or Incorrect Drill Files (6% of rejections)
Common issues: missing NPTH file, mixed plated/non-plated in one file, imperial/metric mismatch, missing back-drill specs. For HDI, each via span needs its own drill file.
Fix: Create a drill file checklist matching your stackup: one file per drill span, clearly named. Include drill span diagram in fabrication drawing.
9. Via-in-Pad Without Specification (5% of rejections)
Designers use via-in-pad without specifying fill type. An unfilled via-in-pad wicks solder during reflow, creating voids under BGA balls.
Fix: Always specify: "Via-in-pad: copper-filled and capped per IPC-4761 Type VII" in fab notes.
10. Solder Paste Stencil Conflicts (4% of rejections)
Paste openings extending beyond mask openings, paste on thermal pads too large (causing tombstoning), or wrong aperture format.
Fix: Paste openings 1:1 with or slightly reduced from mask openings. For large thermal pads, use 50-60% windowed coverage.
11. Panelization Conflicts (3% of rejections)
Boards with overhanging connectors, non-rectangular outlines, or internal cutouts that prevent efficient panelization.
Fix: Include panelization suggestion for unusual geometry. Specify breakaway method and no-tab zones.
12. Silkscreen on Pads (2% of rejections)
Silkscreen ink on exposed pads interferes with solderability.
Fix: 4mil minimum clearance between silkscreen and any pad. Run final DRC after silkscreen placement.
Pre-Submission DFM Checklist
Before exporting Gerber files, verify:
- Annular ring: minimum 5mil on all vias/PTH pads
- No acute angle trace junctions (all 90 degrees or greater)
- Solder mask dams: minimum 3mil between adjacent openings
- No floating copper or unconnected pour islands
- Board edge clearance: 10mil external, 15mil internal
- NPTH anti-pads on ALL copper layers
- Impedance verified with field solver against real prepreg
- Drill files complete: one per span, PTH/NPTH separated
- Via-in-pad fill type specified in fab notes
- Paste layer verified against mask layer
- Panel tab locations identified (irregular boards)
- Silkscreen cleared from all pads by 4mil
This takes 20-30 minutes but saves 1-3 days of review cycles.
Originally published at AtlasPCB Engineering Blog. Every AtlasPCB order includes engineering DFM review — we catch these issues before they become expensive delays. Learn more about our PCB manufacturing capabilities.
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