After processing thousands of incoming Gerber packages per month, we've identified the five verification points that catch 78% of all DFM (Design for Manufacturability) issues. Running through this 15-minute checklist before submitting to your fabricator saves an average of 4 days and $500-2000 per revision cycle.
The 5-Point Quick Check
| Check | What to Verify | Common Failure (% of rejections) |
|---|---|---|
| 1. Gerber Integrity | All layers, correct format, drill files | Missing paste mask/wrong format (18%) |
| 2. Clearance Rules | Trace/space, copper-to-edge | Copper too close to board edge (15%) |
| 3. Via Specifications | Aspect ratio, annular ring | Annular ring below minimum (23%) |
| 4. Impedance Notes | Target Z, reference layers, tolerance | No stackup reference (10%) |
| 5. Mask/Silkscreen | Dam width, text size | Solder bridges on fine-pitch (12%) |
1. Gerber File Integrity
The most frustrating rejection: a missing file. 18% of our first-submission packages arrive incomplete — usually a missing paste mask, an outdated drill file from a previous revision, or a board outline that doesn't match copper layers.
Before zipping your package:
- Open every file in a standalone viewer (not your EDA tool)
- Verify board outline matches on every layer
- Via locations align between drill files and copper pads
- Drill file includes complete tool table with correct sizes
Naming convention matters. Files named "Layer1.gbr" through "Layer10.gbr" with no readme force your fabricator to guess which is top copper vs internal ground. Use explicit names: TopCopper.gbr, InnerGND1.gbr, BottomCopper.gbr.
2. Clearance Rules
Clearance violations are insidious because your EDA DRC may pass with its own rules while the fabricator's actual process capability is different.
Critical clearances to verify:
- Copper-to-board-edge: 0.25mm minimum (routed), 0.5mm (V-scored)
- Drill-to-copper: 0.2mm for mechanical drills, 0.15mm for laser microvias
- Trace-to-trace: Per your design rules, but verify fabricator's minimum
The failure mode: during routing, the router bit has tolerance of +/-0.1mm. Copper at 0.15mm from the edge can get exposed — creating a short-circuit path or corrosion initiation site.
3. Via Specifications — The #1 Rejection Cause
Annular ring failures account for 23% of all DFM rejections. Here's why they're so common:
A 0.3mm drill with 0.55mm pad gives nominal annular ring of 0.125mm (5mil). Sounds comfortable against IPC's 1mil minimum. But factor in:
- Drill positional accuracy: +/-0.05mm
- Pad registration: +/-0.025mm per layer
- Etch compensation variation: +/-0.015mm
Actual annular ring can drop to 0.035mm (1.4mil). Close to the wire for IPC Class 2, below minimum for Class 3.
Practical minimums:
- Standard PTH, Class 2: 4mil (0.1mm) design annular ring
- Standard PTH, Class 3: 5mil (0.125mm)
- Laser microvias (HDI): 2.5-3mil (0.065-0.075mm)
Aspect ratio: Standard mechanical drilling supports up to 10:1 (depth:diameter). For 1.6mm board thickness, minimum 0.16mm drill. Below this = HDI required.
4. Impedance Specifications
A proper impedance callout includes:
- Target value (50 ohm SE, 100 ohm diff)
- Reference layer for each impedance class
- Tolerance (+/-10% standard, +/-5% tight)
- Whether fabricator should adjust trace width OR dielectric thickness
The most productive approach: provide your stackup intent with impedance targets and let the fabricator's engineers optimize the final stackup. They know their actual Dk values (which drift 2-5% from datasheet) and their etch compensation factors.
5. Solder Mask and Silkscreen
Critical parameter: solder mask dam width — the mask material between adjacent pads.
- Below 3mil (75um): mask tears or lifts, creating solder bridges
- 0.5mm pitch BGA: dam is ~8mil — comfortable
- 0.4mm pitch BGA: dam drops to 3-4mil — verify your fab has LDI capability
The Complete Pre-Submit Checklist
- Open all Gerbers in standalone viewer — verify alignment, no blank layers
- Copper-to-edge: minimum 0.25mm routed, 0.5mm V-scored
- Annular ring: minimum 4mil (Class 2) or 5mil (Class 3)
- Drill aspect ratio: diameter > board_thickness / 10
- Impedance table with: target, reference layer, tolerance
- Solder mask dam > 3mil between all adjacent pads
- Fab note file: material, finish, impedance, special requirements
What This Saves You
Based on our data across 6,000+ orders in the past year:
- Average time saved: 4.2 days per order that would have been rejected
- Cost saved: $800-2,000 in re-spin NRE per caught issue
- First-pass rate improvement: Teams using this checklist achieve 94% first-pass acceptance vs 76% average
This checklist is based on production DFM rejection data from our facility processing 500+ unique designs per month. For specific DFM questions about your design, upload Gerber files at AtlasPCB and our engineering team will provide a detailed review.
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