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Posted on • Originally published at atlaspcb.com

RF PCB DFM Handoff Checklist: 12 Items That Prevent Respins on Rogers and PTFE Boards

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After reviewing 500+ RF PCB orders over the past 18 months, we've identified the 12 most common DFM handoff failures that cause respins. 42% trace back to a single issue: specifying Dk at the wrong frequency.

Here's the complete checklist for RF designs using Rogers 4350B, RO4003C, PTFE, and hybrid stackups.

The 12-Item RF DFM Handoff Checklist

# Item What to Specify Failure Rate
1 Material MPN Exact vendor P/N per layer 18%
2 Dk at operating freq Value + frequency + source 42%
3 Df at operating freq Value + frequency 12%
4 Core thickness + tol Nominal + acceptable range 8%
5 Copper weight/type Weight + ED/RA/LoPro treatment 6%
6 Impedance per layer Target + tolerance + ref layer 28%
7 Via fence spec Pitch + diameter + connection 12%
8 Bonding material Prepreg type for hybrid builds 18%
9 Backdrilling Depth + stub length tolerance 5%
10 Test coupon plan Location + structure type 15%
11 Edge plating Where + thickness + continuity 3%
12 Transition notes Via anti-pad, clearance 4%

Note: Failure rates overlap (one order can have multiple issues).

The #1 Problem: Dk at Wrong Frequency

Rogers RO4350B has Dk ≈ 3.66 at 1 MHz (IPC test method) but Dk ≈ 3.48 at 10 GHz (clamped stripline resonator). If you design using Dk = 3.66, your trace will be narrower than optimal. The manufactured board sees Dk = 3.48 at your operating frequency, producing impedance 3-4 ohms higher than target.

The fix: Specify Dk at or near your operating frequency. Cite the measurement method. State what Dk value your impedance calculation assumed.

Impedance: Per-Layer, Not Blanket

Don't specify "All traces: 50 ohm ±10%." Instead, provide a layer-by-layer table:

Layer | Net Class | Target | Tolerance | Trace W | Material
L1    | RF_50     | 50Ω SE | ±5%       | 12.8mil | RO4350B  
L3    | USB3      | 90Ω DF | ±10%      | 4.5mil  | FR-4
L5    | DDR4      | 40Ω SE | ±10%      | 5.0mil  | FR-4
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This tells the manufacturer where to focus process control, potentially reducing cost while improving RF performance.

Hybrid Stackup Bonding: The Missing Specification

For Rogers/FR-4 hybrid builds, 18% of designers completely omit the bonding material specification. This matters because:

  • CTE mismatch: Rogers Z-axis CTE (32 ppm/°C) vs FR-4 prepreg (50-70 ppm/°C) creates stress during thermal cycling
  • Dk at boundary: Standard FR-4 prepreg (Dk ≈ 4.0) vs Rogers bondply (Dk ≈ 3.54) — which one does your model assume?
  • Press compatibility: RO4350B works with standard FR-4 press profiles, but PTFE materials require modified profiles

Copper Roughness: The Hidden Variable

Above 10 GHz, copper surface roughness changes effective Dk by 3-5% and adds 0.5-1.5 dB/inch loss. Standard ED copper (RMS ≈ 5-7 μm) vs LoPro/HVLP (RMS ≈ 1.5-2 μm) is a meaningful difference.

Always specify copper type. For designs >10 GHz, call out "LoPro" or "HVLP" explicitly.

Via Fence Pitch: Lambda/4 Rule

Via fence spacing must be < λ/4 at highest frequency:

  • At 28 GHz (in RO4350B): max pitch ≈ 2.5mm
  • At 77 GHz: max pitch ≈ 0.9mm (requires laser vias)

Don't reuse your digital ground stitching pitch (1-1.5mm) and assume it works for RF isolation at mmWave.

Test Coupon Strategy

For RF boards, generic impedance coupons aren't enough. Consider:

  1. Standard impedance coupon — per controlled net class, same panel location
  2. Through-loss coupon (TRL) — for >10 GHz insertion loss verification
  3. Isolation coupon — two traces with via fencing, measure S21

Key rule: specify "on production panel, within 2 inches of board array" — not on a separate panel with different press conditions.

The Complete Handoff Package

A professional RF PCB handoff includes:

  1. Gerbers (RS-274X or X2)
  2. Drill files (separate for mechanical and laser)
  3. Stackup drawing with material MPNs, Dk/Df at frequency
  4. Layer-by-layer impedance table
  5. IPC netlist
  6. Fab notes (substitution policy, via fill, surface finish)
  7. Test requirements (coupons, cross-section locations)
  8. Critical dimension callout

Missing any of these for an RF board means you'll get questions at best, incorrect assumptions at worst.

Originally published at AtlasPCB Engineering Blog — our RF process engineers review every submission for DFM completeness before manufacturing starts.

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