Originally published at AtlasPCB
TSMC Raises AI Demand Forecast at Technology Symposium
At its North America Technology Symposium held in May 2026, TSMC significantly elevated its long-term outlook for AI-related semiconductor demand, projecting an eleven-fold increase in AI accelerator wafer shipments between 2022 and 2026. The foundry giant also raised its estimate for the total addressable semiconductor market to exceed $1.5 trillion by 2030.
The announcement came alongside detailed roadmaps for expanding CoWoS (Chip on Wafer on Substrate) advanced packaging capacity, SoIC 3D stacking technologies, and silicon photonics integration—all critical enabling technologies for next-generation AI training and inference hardware.
CoWoS Capacity Expansion: What It Means for PCB Substrates
TSMC's CoWoS packaging platform is the enabling technology behind NVIDIA's H100, B200, and GB200/300 accelerators, as well as AMD's MI300 and MI400 series. Each CoWoS package requires:
- High-layer-count PCB substrates (20+ layers with 50μm line/space)
- Ultra-low-loss dielectric materials to support 112Gbps+ SerDes signaling
- Large-format panels (up to 100mm × 100mm substrate size for GB300)
- Precise impedance control across all signal layers (±5% tolerance)
The 11× growth projection means substrate manufacturers must dramatically scale output. Industry reports indicate CoWoS substrate supply remains the primary bottleneck—not wafer fabrication capacity—for AI chip delivery timelines through at least late 2027.
Five 2nm Fabs Ramping Simultaneously
TSMC disclosed that five 2nm wafer fabrication facilities are simultaneously entering ramp-up in 2026—an unprecedented parallel production introduction. First-year 2nm output is projected approximately 45% higher than 3nm production at the equivalent milestone, reflecting the massive pre-orders from AI chip designers.
The Arizona expansion continues as well, with the third Phoenix fab topped out and targeting sub-2nm process technologies with production before 2030. TSMC's board approved up to $20 billion in additional capital investment for its Arizona subsidiary.
For PCB substrate suppliers, this acceleration means:
- Higher demand for ABF (Ajinomoto Build-up Film) substrates
- Increased orders for high-layer-count test boards and interposer carriers
- Growing need for glass-core substrates as silicon interposers exceed current organic substrate capabilities
Market Impact on PCB Supply Chain
TSMC's record 2026 capital expenditure budget of $52-56 billion signals sustained demand growth that cascades through the entire electronics supply chain:
- Substrate manufacturers (Ibiden, Shinko, AT&S) are adding capacity but remain supply-constrained
- CCL/laminate suppliers face pricing pressure as high-end material demand outpaces supply
- PCB fabricators serving AI server OEMs report lead time extensions from 8 to 14 weeks
- Testing capacity for high-speed substrates (>56 Gbps channel verification) remains scarce
The foundry also highlighted that future performance improvements will increasingly rely on advanced packaging, interconnect architectures, and system-level optimization rather than transistor scaling alone—further elevating the importance of PCB substrate technology in the overall chip performance equation.
Technical Implications: What 11× Means for PCB Substrates
The exponential scaling of CoWoS packaging creates specific technical demands on PCB substrate technology:
Larger interposer substrates: Next-generation AI packages use die-stitched silicon interposers exceeding two reticle fields in area. The organic package substrates beneath these interposers must grow correspondingly—from ~55×55mm for current designs to ~100×100mm for GB300-class packages. This pushes organic substrate fabrication panels to their physical limits.
Higher HBM memory integration: Future CoWoS packages will integrate 8-12 HBM stacks per device (up from 4-6 today). Each stack requires precise microbump connections and thermal management paths through the substrate, demanding more redistribution layers with finer features.
Signal integrity at 224 Gbps: Next-generation AI interconnects target 224 Gbps PAM4 signaling between chiplets and to external SerDes. The package substrate and system board must support <15 dB insertion loss at 56 GHz Nyquist frequency—requiring ultra-low-loss dielectrics and precise impedance control throughout the signal path.
Power delivery scaling: AI accelerators dissipating 700-1000W require hundreds of amps delivered through the package substrate. This necessitates thick copper layers (20-35μm), extensive power/ground plane allocation, and low-resistance via structures that compete for routing resources.
Industry Capacity Response
Substrate manufacturers are responding with massive capital investments:
- Ibiden: Expanding Ogaki facility with new clean rooms targeting 2027 full production
- Shinko Electric: Investing ¥130 billion in new Nagano substrate factory
- AT&S: Kulim, Malaysia facility Phase 2 targeting CoWoS-equivalent substrates
- Samsung Electro-Mechanics: Sejong campus expansion for AI substrate production
Despite these investments, industry analysts project substrate supply will lag demand through at least 2027, creating continued allocation pressure for PCB-grade ultra-low-loss materials that share similar resin systems with substrate build-up layers.
AtlasPCB's Position in AI Hardware
As AI hardware continues its exponential growth trajectory, AtlasPCB serves the ecosystem through:
- High-layer-count prototype boards (up to 32 layers) for AI accelerator evaluation platforms
- Advanced HDI fabrication with sequential lamination for substrate-like density
- Ultra-low-loss material processing (Megtron 7, Panasonic R-5775K) for 112G+ SerDes channels
- Rapid-turn prototyping enabling AI chip designers to validate packaging concepts quickly
The growing complexity of AI server PCBs—20+ layers, 50μm features, controlled impedance on every signal layer—demands fabrication partners with deep process expertise and advanced material handling capabilities.
Source: FTC Electronics Weekly News, TSMC North America Technology Symposium presentations, May 2026.
Image: Alexandre Debiève via Unsplash
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