PCB Design Requirements for Edge AI Inference Modules: Thermal, Power, and Signal Integrity

Edge AI packs 50-150W into modules smaller than a credit card. Cloud AI spreads 300-700W across large server boards with unlimited cooling budgets. This density creates three simultaneous engineering constraints that compete for the same stackup real estate.

The Triple Challenge

1. Thermal density: 10-30 W/cm2 under a single package with limited airflow
2. Power delivery: 50-150A at 0.7-1.0V through short, low-impedance paths
3. Signal integrity: LPDDR5 at 6400 MT/s and PCIe Gen5 at 32 GT/s in millimeter routing

More power planes = fewer signal layers. More thermal vias = less routing area. Getting this balance right is the central challenge.

Quick Reference: Edge AI PCB Specs

Parameter	Typical Edge AI	High-Performance Edge
Layer count	8-12	12-16
Power dissipation	15-50W	50-150W
Copper weight (power)	2 oz	3-5 oz
Min trace/space	4/4 mil	3/3 mil
Via type	Microvia + through	Stacked microvia HDI
Memory interface	LPDDR4X/LPDDR5	LPDDR5/LPDDR5X
Board size	70x70mm to 100x100mm	100x100mm to 170x170mm

Thermal Management: Beyond Via Arrays

Thermal Via Array Design

For AI processors dissipating 50-150W through an exposed thermal pad:

Parameter	Minimum	Recommended	Aggressive
Via drill	0.3 mm	0.3 mm	0.25 mm
Via pitch	1.0 mm	0.6 mm	0.5 mm
Via fill	Tented	Non-conductive	Conductive
Thermal R (array)	15 C/W	8 C/W	4 C/W

Design rules:

• Fill ALL thermal vias (IPC-4761 Type V/VII) to prevent solder wicking
• Place vias on same grid as stencil openings
• Connect bottom to continuous copper pour (heat spreader interface)
• No thermal relief on thermal vias — full flood connection

When Arrays Arent Enough

Above 100W in compact form factors (<100x100mm), via arrays alone cannot achieve sufficient thermal resistance. Consider:

• Embedded copper coin: 2-4mm thick copper slug, thermal R: 1-2 C/W, adds $30-80/board
• Metal-core layer: Al or Cu core in stackup center for uniform spreading
• Direct die attach: Skip package TIM, bond die directly to board spreader

Power Delivery Network Design

The PDN Challenge

A typical edge AI ASIC draws:

• Core: 50-100A at 0.75V
• I/O: 10-20A at 1.2V
• Memory: 5-10A at 1.1V

With 5% tolerance on 0.75V, total PDN impedance budget is just 0.375 mOhm — including VRM, decoupling, and planes combined.

12-Layer PDN Stackup Strategy

Layer	Function	Cu Weight
L1	Signal + BGA fanout	1 oz
L2	Ground (reference)	1 oz
L3	Signal (LPDDR5)	0.5 oz
L4	VDD Core	2 oz
L5	Ground	2 oz
L6	VDDIO	2 oz
L7	Ground (isolation)	2 oz
L8	VDDQ	2 oz
L9	Ground (reference)	1 oz
L10	Signal (low-speed)	0.5 oz
L11	Ground (bottom ref)	1 oz
L12	Signal + bottom comp	1 oz

Key principles:

• Every signal layer immediately adjacent to ground (no signal-signal)
• 2oz minimum for 50A+ power planes
• Separate ground between analog and digital domains
• First tier decoupling (0201) within 1mm of BGA power balls

Signal Integrity: Memory and High-Speed

LPDDR5 Routing

Parameter	LPDDR5 (6400 MT/s)	LPDDR5X (8533 MT/s)
Z differential	80-100 ohm	80-100 ohm
Max trace length	25 mm	20 mm
Intra-byte match	+/- 0.5 mm	+/- 0.25 mm
Routing	Stripline preferred	Stripline mandatory
Crosstalk	< -30 dB	< -35 dB

PCIe Gen5

• 85 ohm differential (+/- 10%)
• Max 200mm trace length
• Via stub < 8 mil (backdrilling required)
• Loss budget < 8 dB at 16 GHz

HDI for BGA Fanout

Modern edge AI processors use 0.5-0.65mm pitch BGAs with 600-2000+ balls:

• Layer 1-2 microvias for signal escape
• Stacked microvias (2-3 levels) for power/ground
• Via-in-pad on all BGA pads (IPC-4761 Type VII)
• 3/3 mil minimum trace/space between pads

Typical structure: 2+N+2 or 3+N+3 buildup with 0.1mm laser-drilled microvias.

Material Selection

Tier	Material	Dk (10 GHz)	Df (10 GHz)	Use Case
Standard	High-Tg FR-4	4.2	0.018	LPDDR4, PCIe Gen4
Mid	Megtron 4	3.8	0.008	LPDDR5, PCIe Gen5
High	Megtron 6	3.6	0.004	LPDDR5X, 112G SerDes

Most 2026 edge AI modules operate at mid-range — LPDDR5 + PCIe Gen5 are well served by Megtron 4 class without ultra-premium materials.

Design Checklist

1. Stackup: min 8 layers, 12+ for complex. Every signal layer referenced to ground
2. Power planes: 2oz min for core voltage, separate VDD/VDDIO/VDDQ domains
3. Thermal vias: Filled array under processor, 0.3mm drill, 0.6mm pitch
4. HDI: Via-in-pad for BGA, 2+N+2 minimum for 0.5mm pitch
5. Memory routing: Stripline adjacent to ground, matched within +/- 0.5mm
6. PCIe: 85 ohm differential, backdrilled stubs
7. Decoupling: 0201 within 1mm, bulk within 5mm
8. Board thickness: 1.6-2.0mm typical
9. Surface finish: ENIG for BGA; Immersion Silver for loss-sensitive pads
10. Testing: Impedance coupon + thermal cycling per IPC-6012 Class 3

Practical Takeaway

Edge AI board design is about managing conflicts between thermal, power, and signal requirements. The stackup is your primary tool for resolving these conflicts — every layer assignment is a trade-off decision.

The engineers at AtlasPCB have been fabricating boards combining heavy copper power planes (up to 5oz) with fine-line HDI signal routing (3/3 mil) in the same stackup — which is exactly what these AI modules demand.

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Originally published on the AtlasPCB Engineering Blog.