Originally published on AtlasPCB Engineering Blog. AtlasPCB specializes in multilayer PCB manufacturing from 1 to 30 layers.
Reviewed by AtlasPCB Engineering Team
The Real Question: Is the Extra Cost Worth It?
The jump from four layers to six is the most common layer-count decision that lands in our engineering review queue. Designers know their boards need more than two layers, they have already committed to a multilayer build, and now they face a choice that affects both their bill of materials and their confidence in passing EMC certification on the first attempt.
The short answer is straightforward. If your design includes any BGA with a pitch at or below 0.8 millimeters, any DDR4 or DDR5 memory interface, any serial link running faster than 5 gigabits per second, or if your board area is too tight to route all your nets on two signal layers, you need six layers. For everything else, four layers handle the job at lower cost. The detailed answer requires understanding exactly what those two additional layers give you, what they cost in real production dollars, and where the break-even point falls for your specific design.
At AtlasPCB, we manufacture roughly equal volumes of 4-layer and 6-layer boards across our production lines. The designs that succeed on four layers share common characteristics: moderate pin density, clock frequencies below 200 megahertz, generous board area relative to component count, and interfaces that do not require matched-length differential routing. The designs that need six layers also share patterns, and understanding those patterns before you commit your stackup saves both money and schedule.
Stackup Architecture: What the Extra Layers Provide
A 4-layer PCB stackup uses the standard configuration of Signal-Ground-Power-Signal, placing one reference plane (ground) directly beneath the top signal layer and one reference plane (power) above the bottom signal layer. This gives you two outer routing layers, each with a single adjacent reference plane for impedance control.
A 6-layer PCB stackup in its most common configuration uses Signal-Ground-Signal-Power-Ground-Signal. The critical additions are a third signal layer (L3) buried between the ground and power planes, and a second ground plane (L5) that provides a dedicated reference for the bottom signal layer.
The structural differences are more significant than the simple addition of two copper layers suggests. In a 4-layer board, the two reference planes (L2 ground and L3 power) are separated by the full core thickness, typically 1.0 to 1.2 millimeters. This wide spacing means the power-ground plane pair provides minimal interplane capacitance for power delivery decoupling. In a 6-layer board, the power plane (L4) and its adjacent ground plane (L5) are separated by only 3 to 5 mils of prepreg, creating a tightly coupled capacitor structure that dramatically reduces power distribution network impedance at frequencies from 100 megahertz to over a gigahertz.
The buried signal layer (L3) in a 6-layer board sits between two continuous reference planes — ground above and power below. This configuration is called a stripline environment, and it provides superior noise isolation compared to the microstrip traces on outer layers. Outer-layer microstrip traces radiate energy into the air above them and are susceptible to external electromagnetic interference. The shielded L3 stripline sees neither problem because the reference planes above and below contain the electromagnetic field completely. For sensitive or high-speed signal routing, this shielding advantage alone often justifies the additional cost.
Routing Capacity: When Two Signal Layers Are Not Enough
The most concrete way to evaluate whether you need six layers is to calculate your routing demand against available routing capacity. This calculation depends on your component pin count, BGA pitch, board dimensions, and the minimum trace width and spacing your design requires.
On a 4-layer board, you have two routing layers — the top and bottom surfaces. Every signal must be routed on one of these two layers or transition between them through vias that consume board area and add cost. A standard routing channel between two 0.5-millimeter-pitch BGA pads allows one trace at 4-mil trace width with 4-mil spacing. With two routing layers, you can escape two rows of BGA pins per routing channel before running out of space.
A 0.5-millimeter-pitch BGA with a 15-by-15 array has 225 pads. After placing power and ground pads (typically 30 to 40 percent of total), you have roughly 135 to 155 signal pins that need escape routing. On a 4-layer board with two available signal layers, escaping this many pins from a 0.5mm pitch BGA requires either via-in-pad technology or a large via fanout area surrounding the component, both of which add significant cost and board area. With three signal layers available on a 6-layer board, the same BGA can be escaped more compactly because the interior pins route down to L3 through microvias or through-hole vias, freeing the outer layers for the peripheral pins.
The practical threshold we see in production is this: if your design has fewer than 300 total signal pins on components with pitch at or above 0.65 millimeters, and your board area is at least 1.5 times the component placement area, a 4-layer board provides adequate routing capacity. Once you exceed 400 signal pins, drop below 0.65mm pitch, or have a board area ratio below 1.2, a 6-layer board almost always produces a cleaner layout with shorter trace lengths and fewer vias.
EMI Performance and Signal Integrity
The electromagnetic behavior of a PCB is fundamentally shaped by how completely and consistently the signal traces are referenced to adjacent ground planes. This is where 4-layer and 6-layer boards diverge most significantly for designs operating above 100 megahertz.
On a 4-layer board in the standard S-G-P-S configuration, the top signal layer is referenced to the L2 ground plane and the bottom signal layer is referenced to the L3 power plane. When a signal transitions from the top layer to the bottom layer through a via, the return current must also transition from the ground plane to the power plane. If the ground and power planes are not well connected at that point by decoupling capacitors, the return current finds a long path that creates a loop antenna radiating electromagnetic energy. This return path discontinuity is the single largest source of EMC failures in 4-layer designs.
A 6-layer board addresses this problem from two directions. First, the tightly coupled L4-L5 power-ground pair provides intrinsic interplane capacitance that allows return current to transition between planes without relying solely on discrete decoupling capacitors. Second, the most sensitive signals can be routed on the shielded L3 layer, where they never need to change reference planes and where external noise cannot couple into them.
In our EMC pre-compliance testing at AtlasPCB, we consistently observe that 6-layer boards achieve 6 to 15 dB lower radiated emissions than equivalent 4-layer designs at frequencies above 200 megahertz, assuming competent layout practices on both. For products targeting FCC Class B certification (the stricter consumer standard), this margin often represents the difference between passing on the first test and requiring a board respin.
Power Delivery Network Comparison
The power delivery network performance gap between 4-layer and 6-layer boards is substantial and often underestimated during the design phase. Modern digital ICs switch large transient currents at frequencies from tens of megahertz to several gigahertz, and the PCB plane structure must supply those currents with minimal voltage fluctuation.
In a 4-layer board, the ground plane (L2) and power plane (L3) are separated by the core laminate, typically 1.0 to 1.2 millimeters thick. The interplane capacitance of this pair is approximately 25 picofarads per square centimeter — enough to provide some high-frequency decoupling, but not enough to maintain low impedance above 100 megahertz without extensive discrete capacitor placement. Engineers compensating for this limitation must place more decoupling capacitors, use larger capacitor values, and pay careful attention to capacitor mounting loop inductance. The board area consumed by these capacitors can be significant.
In a 6-layer board, the L4-L5 power-ground pair is separated by only 3 to 5 mils of prepreg, creating interplane capacitance of approximately 500 to 800 picofarads per square centimeter — a twenty-fold improvement. This embedded capacitance provides effective decoupling at frequencies from approximately 200 megahertz to over 1 gigahertz without discrete components. The practical result is that a 6-layer board typically needs 30 to 50 percent fewer decoupling capacitors than a 4-layer board for the same target PDN impedance, which partially offsets the higher bare-board cost through reduced BOM cost and simplified assembly.
Interface-by-Interface Decision Table
Rather than applying general rules, the most reliable way to choose your layer count is to evaluate each interface on your board against its specific requirements. The following recommendations are based on our manufacturing and signal integrity experience across thousands of production designs.
For USB 2.0 operating at 480 megabits per second, a 4-layer board is fully adequate. The differential pair requires 90-ohm impedance and benefits from a continuous ground reference, both of which a standard 4-layer stackup provides. USB 3.0 at 5 gigabits per second can work on 4 layers if the differential pair routing is short (under 100 millimeters) and well-isolated, but a 6-layer board provides better margin. USB 3.2 Gen 2 at 10 gigabits per second and USB4 should use 6 layers, with the differential pairs routed on the shielded internal layer.
Ethernet interfaces follow a similar pattern. 10/100BASE-T and Gigabit Ethernet work well on 4-layer boards. 2.5GBASE-T benefits from 6 layers for the improved differential pair environment. 5GBASE-T and 10GBASE-T require 6 layers as a minimum, with careful attention to impedance control and crosstalk management.
PCIe Gen 3 at 8 gigatransfers per second can be implemented on 4 layers for single-lane interfaces with short traces. PCIe Gen 4 at 16 gigatransfers per second should use 6 layers. PCIe Gen 5 at 32 gigatransfers per second is best served by 8 layers or more, though carefully designed 6-layer implementations with premium materials can work for single-lane connections.
DDR4 memory interfaces should use 6 layers as a standard practice. While simple DDR4-2133 implementations have been done on 4 layers, the layout complexity and signal integrity risk are disproportionate to the board cost savings. DDR5, with its higher data rates and tighter timing margins, requires 6 layers as an absolute minimum and benefits from 8 layers for dual-rank configurations.
HDMI 2.0 at up to 18 gigabits per second aggregate bandwidth benefits from 6 layers for the TMDS differential pairs. HDMI 2.1 at 48 gigabits per second should use 6 layers with careful material selection, potentially requiring low-loss laminates for longer trace runs.
Real Manufacturing Cost Breakdown
Understanding where the cost comes from helps you make informed trade-offs rather than simply reacting to a quoted price. The manufacturing process for a 6-layer board involves specific additional steps compared to a 4-layer board, and each step adds a quantifiable cost increment.
A 4-layer board requires one inner-layer imaging and etching cycle (for L2 and L3), one lamination press cycle, outer-layer processing (drilling, plating, imaging, etching), and finishing. A 6-layer board adds a second inner-layer imaging and etching cycle (for the additional L2/L3 pair in the construction), a second lamination press cycle (or a more complex single-cycle press with additional layup), and tighter registration requirements that reduce first-pass yield by approximately 2 to 5 percent.
For a standard 100 by 100 millimeter board in FR-4 with 1-ounce copper and ENIG surface finish, our typical production pricing shows the following relationship. At 10 pieces, a 4-layer board costs approximately $9 to $12 per unit and a 6-layer board costs $14 to $20 per unit, representing a 55 to 67 percent premium. At 100 pieces, the 4-layer costs approximately $4 to $6 per unit and the 6-layer costs $6 to $9 per unit, a 50 to 55 percent premium. At 1,000 pieces, the 4-layer costs approximately $1.80 to $2.50 per unit and the 6-layer costs $2.70 to $3.80 per unit, a 45 to 52 percent premium.
For larger boards at 150 by 200 millimeters, the material cost becomes a more significant fraction of total cost. The premium for 6 layers over 4 drops to approximately 40 to 50 percent at prototype quantities because the additional processing steps are spread over a larger panel utilization. Conversely, for very small boards under 50 by 50 millimeters, the per-unit premium is higher in percentage terms because the fixed setup and processing costs dominate.
Lead time also differs. A standard 4-layer board typically ships in 5 to 7 working days from our facility, while a 6-layer board requires 7 to 10 working days due to the additional lamination and processing cycles. Quick-turn options are available for both, but the express premium for 6-layer boards is proportionally higher because the bottleneck is lamination press capacity, which cannot be easily accelerated.
The Hidden Cost of Choosing Too Few Layers
The most expensive PCB decision is not choosing six layers when you should have — it is choosing four layers and discovering the mistake after your first prototype fails EMC testing or exhibits signal integrity problems in the field.
An EMC test failure at a certified lab typically costs $3,000 to $8,000 per session, including setup, testing, and the engineer's report. If the root cause is inadequate reference plane coverage or return path discontinuities — problems fundamentally caused by insufficient layer count — the fix requires a board respin. A complete respin cycle (layout modification, new Gerbers, fabrication, assembly, and re-testing) adds four to eight weeks and $5,000 to $15,000 to your project cost, depending on BOM complexity and test lab availability.
Compare that to the incremental cost of specifying six layers from the start. For a typical production run of 500 boards at 100 by 100 millimeters, the difference between 4-layer and 6-layer is approximately $1,500 to $2,500 total. If there is any reasonable doubt about whether four layers will meet your EMC requirements, the six-layer option is the financially rational choice before factoring in schedule risk.
We track the reasons for board respins across our customer base, and layer count under-specification accounts for roughly 12 to 15 percent of first-revision failures. The most common failure modes are radiated emissions above the FCC Class B limit at harmonics of the main clock frequency, power supply noise coupling into sensitive analog circuits through the poorly-decoupled power-ground plane pair, and DDR memory timing failures caused by excessive crosstalk on unshelded outer-layer routing.
Design Rules and DFM Considerations
The manufacturing process capabilities for 4-layer and 6-layer boards are largely identical at standard technology levels, but the tighter registration requirements of 6-layer boards affect some design rules in practice.
For trace width and spacing, both layer counts support the same minimums at a given fabricator — typically 3.5 to 4 mil trace width and spacing for standard process, or 3 mil for advanced process. However, the additional inner layers in a 6-layer board must account for registration tolerance between the inner-layer artwork and the drilled holes. Our standard layer-to-layer registration tolerance is plus or minus 3 mils for conventional multilayer boards. This means that the minimum annular ring for inner-layer pads must accommodate the registration tolerance in addition to the drill tolerance. For a 10-mil drill hole with 3-mil registration tolerance and 1-mil drill wander, the minimum pad diameter is 18 mils (10 + 2 x 3 + 2 x 1) to guarantee a 1-mil annular ring on all inner layers.
Via structure is another consideration. Through-hole vias in a 4-layer board pass through all four layers, which is straightforward. In a 6-layer board, through-hole vias also pass through all six layers, but the longer via barrel means the via acts as a more significant impedance discontinuity for high-speed signals. For designs with signal speeds above 5 gigabits per second, the via stub created by a through-hole via in a 6-layer board (where the signal enters on L1 and transitions to L3) can cause resonant notches that degrade signal quality. Backdrill technology removes the unused via stub, but it adds approximately 15 to 25 percent to fabrication cost.
For thermal management, both layer counts provide similar options through thermal vias and copper pours. The additional copper layers in a 6-layer board do provide more thermal spreading capacity, which can be significant for designs with concentrated heat sources like power regulators or high-performance processors.
When Four Layers Are Enough
Despite the advantages of six layers, many designs are perfectly served by a 4-layer stackup, and choosing four layers in these cases saves real money without technical compromise.
Microcontroller-based designs running at clock frequencies below 100 megahertz with moderate pin counts (fewer than 200 signal pins) route cleanly on two signal layers. Power supply and motor driver boards where the primary routing challenge is wide power traces rather than dense signal routing benefit from the simplicity and lower cost of four layers. IoT sensor modules with wireless connectivity (WiFi, BLE, LoRa) typically have low pin-count SoCs and antenna structures that are well-served by a 4-layer board with careful ground plane design. Industrial control boards with relay drivers, optocouplers, and simple serial interfaces rarely need more than two routing layers.
The key indicators that four layers will work are: all interfaces operating below 1 gigabit per second, no BGA packages with pitch below 0.8 millimeters, board area at least twice the component footprint area, and no stringent EMC requirements beyond basic CE marking with standard mitigation techniques.
When to Skip Straight to Eight Layers
At the other end of the spectrum, some designs should bypass the 6-layer option entirely and move directly to 8-layer or higher stackups.
Designs with dual-channel DDR5 memory running at 4800 megatransfers per second or above need the additional routing layers and reference planes that an 8-layer board provides. Multi-lane PCIe Gen 5 interfaces at 32 gigatransfers per second demand the signal integrity margin of stripline routing with low-loss materials, which is easier to achieve with the additional reference planes available in an 8-layer stackup. Dense FPGA designs with BGA packages at 0.4 millimeters pitch and pin counts above 500 typically cannot be routed within the constraints of three signal layers and need four or more.
The cost jump from 6 to 8 layers (approximately 30 to 40 percent additional) is proportionally smaller than the jump from 4 to 6 layers, so the financial case for moving up is often easier to justify when the technical requirements are clear.
Making the Decision: A Practical Framework
If you have read this far and still are not certain whether four or six layers is the right call for your design, apply this sequential test. First, check your fastest interface. If anything on the board runs at or above 5 gigabits per second, choose six layers. Second, count your BGA signal pins. If any single BGA has more than 100 signal pins at 0.8 millimeters pitch or finer, choose six layers. Third, estimate your routing density. If your total net count exceeds 200 and your board area is below 80 square centimeters, choose six layers. Fourth, assess your EMC requirements. If you need to pass FCC Class B or CISPR 32 Class B without ferrite beads and common-mode chokes on every cable, choose six layers.
If none of these conditions apply, four layers serve your design well at a meaningfully lower cost. The savings are not just in the bare board price — a 4-layer design is simpler to lay out, faster to fabricate, and easier to modify during prototyping iterations.
The layer count decision should be made during the schematic phase, before component placement begins. Changing from four layers to six after layout has started requires significant rework of the stackup definition, impedance targets, and potentially the component placement to accommodate the changed via structures. Getting it right the first time, using the criteria in this guide, eliminates one of the most common and costly missteps in the PCB design process.
This article was originally published on AtlasPCB.com. For a free DFM review of your multilayer design, visit atlaspcb.com/get-quote.
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