The transition from a 6-layer to an 8-layer PCB stackup represents a meaningful step in both design capability and manufacturing cost. After fabricating tens of thousands of 8-layer panels, we've identified when the upgrade is necessary — and when it's over-engineering.
When You Actually Need 8 Layers
The clearest indicator is the simultaneous presence of multiple high-speed interfaces that each require dedicated impedance-controlled routing layers with adjacent solid reference planes. A design carrying DDR4 memory, PCIe Gen4, USB 3.2, and Gigabit Ethernet genuinely needs four signal layers with proper reference plane adjacency.
Other valid reasons:
- Two or more fine-pitch BGAs (0.65mm pitch, 300+ pins) requiring escape routing on multiple layers
- Power distribution requiring complete electrical isolation between domains (separate analog/digital supplies)
- EMC testing failures on 6-layer prototypes indicating insufficient shielding
When 8 Layers Is Over-Engineering
Approximately 35% of the 8-layer boards we manufacture could function as 6-layer designs with modified routing strategies. For boards smaller than 50x50mm, 6 layers with HDI (blind/buried vias) often achieves the same routing density at lower total cost. The 30-50% cost premium over 6-layer should purchase measurable performance improvement, not just engineering convenience.
Three Proven Configurations
Configuration A: Standard Mixed-Signal (Recommended)
L1 - Signal (Top) → Microstrip ref to L2
L2 - Ground Plane → Reference for L1, L3
L3 - Signal (Inner) → Stripline ref to L2, L4
L4 - Power Plane → Reference for L3
L5 - Ground Plane → Reference for L6
L6 - Signal (Inner) → Stripline ref to L5, L7
L7 - Power Plane → Reference for L6
L8 - Signal (Bottom) → Microstrip ref to L7
This provides four signal layers with every layer having at least one adjacent reference plane. Optimal for DDR4, PCIe Gen3, USB 3.0/3.1, and standard mixed-signal designs.
Standard 1.6mm construction (Shengyi S1000-2M):
- L1-L2 prepreg: 0.11mm (1080 glass)
- L2-L3 core: 0.20mm (2116 glass)
- L3-L4 prepreg: 0.11mm (1080 glass)
- Center core (L4-L5): 0.20mm
- Symmetric from center outward
Configuration B: High-Speed Signal Integrity
L1 - Signal → ref to L2
L2 - Ground → ref for L1, L3
L3 - Signal → ref to L2, L4
L4 - Ground → ref for L3, L5
L5 - Power → ref for L6
L6 - Signal → ref to L5, L7
L7 - Ground → ref for L6, L8
L8 - Signal → ref to L7
For PCIe Gen4/Gen5, DDR5, 25G+ SerDes. Three ground planes provide the most predictable impedance environment. Trade-off: only one power plane, so all rails share a single layer.
Configuration C: Power-Dense Multi-Rail
L1 - Signal
L2 - Ground
L3 - Power 1 (3.3V, 5V)
L4 - Signal (inner)
L5 - Signal (inner)
L6 - Power 2 (1.8V, 1.2V)
L7 - Ground
L8 - Signal
For industrial controllers and automotive ECUs requiring isolated power domains. Route only low-speed signals on L4/L5 — they reference power planes, not ground.
Impedance Control: The Numbers
For the standard 1.6mm stackup with 0.11mm prepreg (Dk ≈ 4.2):
Outer layers (microstrip):
- 50Ω single-ended: ~4.2mil trace width (1oz copper)
- 100Ω differential: 4.0mil traces, 4.5mil spacing
Inner layers (stripline):
- 50Ω single-ended: ~4.8mil trace width (0.5oz copper)
- 100Ω differential: 4.0mil traces, 5.5mil spacing
Standard tolerance: ±10%. High-speed option: ±8% (5-10% cost premium).
Material Selection Quick Guide
| Speed Range | Material | Dk/Df at 1GHz | Cost vs FR-4 |
|---|---|---|---|
| < 5 Gbps | Shengyi S1000-2M | 4.25 / 0.019 | 1x (baseline) |
| 5-15 Gbps | Panasonic Megtron 4 | 3.8 / 0.005 | 2-2.5x |
| 5-15 Gbps | Isola 370HR | 3.92 / 0.021 | 1.5x |
| 15+ Gbps | Panasonic Megtron 6 | 3.4 / 0.002 | 4-6x |
Don't upgrade material unless your channel loss budget requires it. Standard FR-4 handles far more than many engineers assume.
Via Strategy: Cost vs Performance Trade-offs
Through-hole (standard): Cheapest. Works for signals below 5 Gbps. Min hole 0.20mm for 1.6mm boards (8:1 aspect ratio).
Back-drilling: For 5-10 Gbps signals where through-hole stubs cause resonance. Adds ~10% to cost.
Blind vias (L1-L2, L7-L8): Useful for BGA escape routing. Adds 15-25% to cost.
Buried vias: Most expensive option (+40-80%). Justified only when routing density makes them physically necessary.
Our recommendation for most designs: through-hole vias with selective back-drilling where needed.
Common Mistakes We See in Production
Asymmetric stackups causing warpage during reflow. Board bows as little as 0.75% can cause BGA open joints at 0.5mm pitch.
High-speed signals on L4/L5 in Configuration C — these reference power planes that often contain splits, creating return path discontinuities.
Low copper density on inner layers causing thickness variation. Maintain ≥40% copper density on all layers (add non-functional fill).
Impedance requirements not in fab drawing — only stated in the EDA tool. Your manufacturer works from Gerber/ODB++ and the fab drawing, not your schematic.
Heavy copper on select inner layers (e.g., 2oz on one power plane, 0.5oz elsewhere) — creates registration challenges. Keep inner copper uniform.
Cost Reality
8-layer vs 6-layer at prototype quantities: 30-50% premium
At production (1000+ boards): 25-40% premium
The premium comes from:
- One additional lamination press cycle (+15-20%)
- Two more imaging/etching operations (+8-12%)
- Tighter registration tolerances
Cost optimization tips:
- Standard 1.6mm thickness (non-standard requires custom materials)
- Through-hole vias only if signal speeds allow
- Standard FR-4 unless channel loss demands upgrades
- Uniform copper weight on inner layers
- Board dimensions optimized for panel utilization
When to Consider Alternatives
- 6-layer with HDI can match 8-layer routing density for small boards (< 40mm × 40mm) at similar cost
- 10-layer justified only when 8-layer routing is genuinely impossible — the cost jump is smaller than 6→8 since the infrastructure is already in place
For a complete deep-dive with specific material part numbers, fab note templates, and worked impedance calculations, see the full guide on our site.
We also have companion guides for 4-layer, 6-layer, and 16-layer stackup design.
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