Originally published on AtlasPCB Engineering Blog
The phrase "HDI circuit board" gets used loosely in the industry — sometimes to describe any board with blind vias, other times reserved for sequential-lamination builds with laser-drilled microvias. The distinction matters because it determines your fabrication process, cost structure, and design rules. This guide covers what HDI actually means from a manufacturing standpoint, when you genuinely need it, and how to specify the right tier for your design.
What Defines an HDI Circuit Board
High density interconnect is not simply a board with more layers. The defining characteristics are structural: laser-drilled microvias (typically 75-150μm capture pad diameter), sequential lamination cycles that build up layers one or two at a time after the core is fabricated, and the routing density these enable — typically 3/3mil trace/space or finer on buildup layers.
A conventional multilayer PCB is fabricated in a single press cycle. All layers are etched, then laminated together with prepreg in one shot. Through-holes are mechanically drilled through the entire stack. This approach works well up to a point, but it imposes fundamental limitations. Mechanical drill bits cannot reliably produce holes smaller than 200μm (8mil). Through-holes consume real estate on every layer they pass through, creating routing blockages even on layers where no connection is needed.
HDI circuit boards solve both problems. Microvias connect only adjacent layers — a blind via from layer 1 to layer 2 does not affect layers 3 through 8. This frees routing channels on inner layers. And because CO₂ or UV lasers drill these vias, diameters of 75-100μm are routine production capability, with capture pads as small as 200μm.
The practical result: where a standard 12-layer board might achieve 40% routing utilization due to through-hole blockages, an equivalent 8-layer HDI design can reach 70-80% utilization. Fewer layers, better signal integrity, often comparable cost.
The Sequential Lamination Process
Understanding HDI tiers requires understanding the fabrication sequence. Each "step" in the nomenclature (1+N+1, 2+N+2, etc.) represents one complete cycle of:
- Laminating prepreg and copper foil onto the existing structure
- Laser drilling microvias through the new dielectric
- Desmearing and cleaning via bottoms
- Electroless copper seeding
- Pattern plating to fill vias and form traces
- Planarizing the surface flat for the next cycle
Each cycle adds 2-3 days to fabrication lead time and 35-50% to per-layer cost. This is why specifying more HDI steps than necessary is expensive, but specifying too few forces compromises in routing or signal integrity.
1-Step HDI (1+N+1)
The entry point into HDI. One buildup layer per side, with microvias connecting layer 1 to layer 2 and layer N-1 to layer N. The core layers (the "N" in the middle) are fabricated conventionally with through-holes.
This structure handles 0.65mm BGA fanout comfortably. A 0.65mm pitch BGA with via-in-pad needs approximately 350μm pad diameter — achievable with a single microvia layer routing outward from the BGA array before dropping through the core via mechanical through-holes.
Typical applications include consumer electronics with mid-density processors, DDR4/DDR5 memory routing, and designs where board thickness constraints make through-hole aspect ratios marginal.
2-Step HDI (2+N+2)
Two buildup layers per side. This introduces the choice between staggered and stacked microvias — a decision with significant cost and reliability implications.
Staggered microvias offset each successive via from the one below, landing on a pad that also serves as a routing channel. This is the lower-cost option because it does not require copper-filling the first-layer via before building the second layer. However, it consumes more lateral space because each via needs a separate landing pad.
Stacked microvias place the second-layer via directly on top of the first-layer via, creating a vertical tower. This requires copper-filling and planarizing the first-layer via before the second lamination cycle (you cannot laser-drill into an air-filled via). Stacked structures provide the highest density and shortest electrical path but add process complexity and cost.
2-step HDI handles 0.5mm BGA pitch and below. It is the workhorse structure for smartphones, tablets, and mid-range compute platforms.
3-Step and Beyond: Any-Layer Interconnect
At 3-step (3+N+3) and above, the design transitions to any-layer interconnect — where every layer in the stack connects to every other layer through stacked microvia towers. There are no conventional through-holes; the entire board is built sequentially.
This is the domain of mobile application processors (0.35-0.4mm BGA pitch), AI accelerator substrates, HBM interposers, and designs where pin count exceeds what lower-tier HDI can fan out.
AtlasPCB supports up to 7-step sequential lamination (7+N+7), handling the most complex substrate-like PCB builds. Each additional step pushes capability but also pushes cost and lead time proportionally.
When Standard Multilayer Falls Short
The decision to move from standard multilayer to HDI is rarely arbitrary. Three engineering thresholds typically force the transition:
BGA Pitch Below 0.65mm
A 0.65mm pitch BGA with 400+ pins cannot fan out through a standard via field. Mechanical drill minimum diameter (200μm) plus annular ring (75μm per side) produces a 350μm finished hole that simply will not fit between 0.65mm pads without violating clearance rules. Via-in-pad with microvias is the only solution that maintains signal integrity without adding routing layers.
Aspect Ratio Constraints
A 2.0mm thick board with 200μm through-holes has a 10:1 aspect ratio — at the limit of reliable plating. If your design needs more layers (pushing thickness higher) or smaller holes (for finer-pitch components), standard drilling hits a wall. HDI microvias penetrate only one dielectric layer (typically 60-80μm), giving aspect ratios well below 1:1 — trivial for modern plating chemistry.
Layer Count Economics
Sometimes HDI is simply cheaper. A design that requires 16 layers in standard construction (due to through-hole routing blockages) might achieve the same connectivity in 10 layers with 1+N+1 HDI. The per-layer cost of HDI is higher, but 10 HDI layers can cost less than 16 standard layers. Your fabricator should provide both quotes for comparison.
Microvia Reliability: What Matters in Production
Not all microvias are created equal. Reliability depends on several manufacturing parameters that should be specified or verified:
Via Fill Quality
For stacked structures, the first-layer microvia must be filled completely with copper — no voids, no dimples exceeding 5μm. Incomplete fill creates a weak landing pad for the next microvia, leading to barrel cracks under thermal cycling. Specify IPC-4761 Type VII (filled and capped) for stacked via applications.
Aspect Ratio Control
Even though microvia aspect ratios are low (typically 0.8:1 to 1:1), the absolute dimensions are small. A 75μm via in 65μm dielectric requires precise laser energy control. Too much energy and the via is overdrilled (potentially damaging the target pad); too little and residual dielectric at the bottom prevents reliable copper bonding.
Desmear Process
After laser drilling, resin residue (smear) coats the via bottom. This must be completely removed before copper seeding. Inadequate desmear is the most common root cause of microvia failure in thermal cycling tests. Verify your fabricator uses permanganate or plasma desmear appropriate to the dielectric material — high-Tg FR-4, Megtron, and polyimide each require different chemistry.
Thermal Cycling Performance
IPC-TM-650 2.6.26 specifies the test methodology for microvia reliability. Industry standard is 6x reflow simulation followed by 1000 thermal cycles (-55°C to 125°C) with less than 10% resistance change. For automotive or aerospace applications, ask for IST (Interconnect Stress Testing) data from your fabricator on the specific stackup and via structure you need.
Design Rules by HDI Tier
Each HDI tier unlocks specific design capabilities while imposing constraints on the designer:
1-Step (1+N+1)
- Minimum via diameter: 100μm (standard), 75μm (advanced)
- Capture pad: 250-300μm
- Trace/space on buildup layers: 75/75μm (3/3mil)
- BGA pitch capability: 0.65mm and above
- Maximum aspect ratio (core): 10:1 with mechanical drilling
- Via-in-pad: yes, but only on outer two layers
2-Step (2+N+2)
- All 1-step capabilities plus:
- Stacked via towers through two buildup layers
- Trace/space: 50/50μm achievable on buildup layers
- BGA pitch: 0.5mm
- Requires copper fill on first-step vias (if stacking)
- Core through-holes still available for power distribution
3+ Step (Any-Layer)
- All 2-step capabilities plus:
- Via connections between any two adjacent layers
- No conventional through-holes (entire stack is sequential)
- Trace/space: 40/40μm on advanced processes
- BGA pitch: 0.4mm and below
- Via landing pad: 175-200μm
Cost Optimization Strategies
HDI does not have to be expensive if you design for manufacturability:
Minimize Sequential Steps
Every additional step multiplies cost. If your design needs via connections spanning three layers, consider whether a buried via in the core (mechanical drill) combined with 1-step buildup microvias can replace a more expensive 3-step full-sequential approach.
Use Staggered Where Possible
Stacked microvias require copper fill — an additional process step. Staggered vias only require standard plating. If your density allows the lateral offset, staggered structures save 10-15% on buildup layer costs.
Optimize Core Layer Count
The core layers in an HDI stack are fabricated conventionally — they are the cheap part. Adding two core layers is often less expensive than adding one buildup step. Work with your fabricator to find the optimal split between core and buildup for your specific design.
Panel Utilization
HDI boards with many sequential steps have higher scrap rates. Design your board outline to maximize panel utilization, reducing the effective per-board cost. Standard HDI panels are 18x24" or 21x24" — your fabricator can advise on optimal dimensions.
Selecting the Right HDI Manufacturer
Not all PCB fabricators are equal in HDI capability. Key qualification criteria include:
Sequential lamination experience — Ask how many years they have produced the specific step count you need. A factory that does 1-step HDI in volume may struggle with 4-step any-layer builds.
Laser drilling equipment — CO₂ lasers are standard for via diameters above 75μm. UV lasers (Nd:YAG at 355nm) are needed for sub-75μm and copper-direct drilling. Confirm your fabricator has the right equipment for your via specifications.
Registration capability — Each sequential lamination introduces registration error. Cumulative tolerance must be managed to ±25μm layer-to-layer (versus ±50μm for standard processes). Ask about their layer-to-layer registration data on recent production lots.
Fill and planarization — For stacked vias, copper fill quality is non-negotiable. Ask for cross-section photos from recent production showing fill completeness and dimple height.
At AtlasPCB, we support 1-step through 7-step sequential lamination with production quantities from a single prototype through volume. Every HDI order receives engineering review to verify your stackup, via structures, and design rules are optimized for both performance and manufacturability.
Common HDI Design Mistakes
After reviewing thousands of HDI designs, certain mistakes recur frequently:
Over-specifying HDI tier. Engineers sometimes request 2-step when 1-step suffices, or stacked when staggered works. This adds unnecessary cost. Start with the minimum HDI tier that satisfies your BGA fanout requirements and only escalate if routing capacity is insufficient.
Ignoring core via optimization. Through-holes in the core layers are cheap and reliable. Use them for power distribution, ground stitching, and connections between inner layers. Reserve microvias for the outer-layer BGA fanout where they are genuinely needed.
Insufficient annular ring on microvia landing pads. Laser registration tolerance plus lamination shift can consume 25-50μm of your landing pad margin. Specify landing pads at least 50μm larger than your via diameter (measured per side) to ensure reliable connections after manufacturing tolerance.
Via-in-pad without specifying fill type. Simply stating "via-in-pad" in fabrication notes is insufficient. Specify whether you need Type V (tented and plugged), Type VI (plugged and planarized), or Type VII (filled and capped). For BGA applications, Type VII is almost always required to prevent solder wicking and voiding.
Conclusion
HDI circuit boards represent a fundamental shift in PCB fabrication methodology — from single-press to sequential-build, from mechanical to laser drilling, from through-hole-dominated to microvia-dominated interconnect. The technology enables the component density that modern processors, memory, and RF devices demand.
The key decision for engineers is not whether HDI is necessary — BGA pitch and pin count will answer that clearly — but which tier provides the optimal balance of density, reliability, and cost. Work with a qualified HDI manufacturer early in the design phase to establish the right stackup before layout begins, and the entire process becomes predictable.
If you're designing HDI boards and want fabrication input before layout, AtlasPCB's engineering team reviews every HDI order for stackup optimization and via structure reliability — from 1-step through 7-step sequential lamination.
Top comments (0)