DEV Community

Cover image for HDI PCB Cost Breakdown: What Drives Pricing from 1+N+1 to 5+N+5
AtlasPCBEngineering
AtlasPCBEngineering

Posted on • Originally published at atlaspcb.com

HDI PCB Cost Breakdown: What Drives Pricing from 1+N+1 to 5+N+5

HDI (High Density Interconnect) PCBs cost anywhere from 1.5x to 12x the price of an equivalent conventional board. The spread is enormous because the cost depends heavily on specific build parameters. Here's a detailed breakdown of what actually drives HDI pricing — and practical strategies to reduce cost by 20-40% without sacrificing functionality.

Cost Overview: HDI vs Conventional PCB

Configuration Complexity Cost Multiplier Typical 10-Layer Price (5pc, 100x100mm)
Conventional (through-hole only) Baseline 1.0x $80-120
1+N+1 (basic HDI) Low 1.5-1.8x $150-200
2+N+2 (standard HDI) Medium 2.5-3.5x $250-400
3+N+3 (advanced HDI) High 4-6x $400-700
4+N+4 Very high 6-9x $600-1,000
5+N+5 / Any-layer (ELIC) Maximum 8-12x $800-1,400

These ranges are for standard FR-4, ENIG finish. Production volumes (1000+ pieces) reduce the per-unit premium significantly.

The Five Primary Cost Drivers

1. Sequential Lamination Cycles (Biggest Impact)

Each "+" in the HDI buildup notation represents a sequential lamination cycle — the board goes back through the entire inner-layer imaging, lamination, and drilling sequence. This is the single largest cost driver because it effectively multiplies the core manufacturing process.

A conventional 10-layer board completes inner layer processing in one pass. A 2+N+2 version goes through lamination three times: once for the 6-layer core, once to add outer buildup layers, and once more to add the second buildup. Each cycle adds 1-2 days and requires precise alignment (±25μm registration between cycles).

Cost impact: roughly 30-50% per additional cycle because you're paying for the panel to be processed through the factory floor multiple times.

2. Microvia Type and Fill Method

Not all microvias are equal from a cost perspective:

Staggered (offset) microvias — Cheapest. Each layer offset from the one below, landing on solid copper. No via filling required. Standard plating is sufficient.

Filled and capped microvias — Moderate cost. Copper-electroplated to completely fill the hole, then planarized flat. Required for via-in-pad or stacking. Adds 45-90 minutes dedicated plating per panel plus grinding.

Stacked microvias — Highest cost. Multiple layers aligned vertically, each drilled into filled copper below. Requires 100% fill quality inspection via cross-section. Cost difference: typically 20-30% of total board price for stacked vs. staggered.

3. Minimum Feature Size

Laser drill diameter affects throughput and yield:

  • 100μm microvias: standard, no premium
  • 75μm: yield drops slightly, +10-15%
  • 50μm (WLCSP/flip-chip): +40-60%, many shops decline

Similarly for trace/space:

  • 100/100μm (4/4mil): standard process
  • 75/75μm (3/3mil): +10-15%
  • 50/50μm (2/2mil): +40-60% (semi-additive process)

4. Board Size and Panel Utilization

HDI panels run through expensive sequential lamination equipment on fixed panel sizes (typically 18x24"). Your board's outline determines pieces per panel, and you pay per panel-pass.

  • 30x30mm module: 30+ pieces/panel (cheap per-unit)
  • 200x150mm mainboard: 4 pieces/panel (expensive per-unit)

Sweet spot: 20x20mm to 80x80mm board area.

5. Material Selection

  • Standard FR-4 (Tg 150): baseline
  • High-Tg (Tg 170): +5-10%
  • Low-loss (Megtron 6): +30-50%
  • Rogers hybrid with HDI: +80-150%
  • Halogen-free: +5-8%

Budget Optimization: 4 Practical Strategies

Strategy 1: Reduce Buildup When Possible

Challenge your HDI assumptions. We regularly review designs where engineers specified 2+N+2 but could achieve the same breakout with 1+N+1 using slightly wider traces on core layers. The cost difference for a 10-layer board: typically $100-200 at prototype quantities.

Strategy 2: Asymmetric Buildups

If high-density components concentrate on one side (common for SoC-centric designs), specify 2+N+1 instead of 2+N+2. Saves 15-25% vs. symmetric.

Strategy 3: Increase Microvia Diameter

Moving from 75μm to 100μm microvias: faster drilling, better yield, 10-15% savings. If your trace/space allows it, the larger via has zero functional downside for most applications.

Strategy 4: Production Volume Leverage

HDI economics improve dramatically at volume. Setup costs are fixed per lot, not per board. The crossover where HDI becomes comparable to just adding conventional layers is typically 200-500 pieces for 1+N+1.

At 5,000+ pieces, a 1+N+1 HDI that consolidates a 12-layer conventional into 8-layer HDI can actually be cheaper per unit — you're paying for fewer total layers.

When HDI Is Actually Worth the Premium

The decision to use HDI should be driven by:

  1. Routing necessity: BGA pitch ≤0.65mm with high pin count cannot break out without microvias
  2. Total system cost: HDI enables smaller boards → smaller enclosure → lower total BOM
  3. Signal integrity: Shorter via stubs for 25+ Gbps signaling
  4. Layer consolidation: 12L conventional → 8L HDI reduces total manufacturing cost at volume

When to avoid HDI: If dog-bone breakout works, if you have board space for more conventional layers, or if production volume <50 pieces and redesigning for conventional routing takes less time than the cost premium justifies.

Do You Actually Need HDI? (BGA Pitch Guide)

  • 0.8mm pitch: Usually escapable with conventional vias (creative routing)
  • 0.65mm pitch: Typically needs 1+N+1 minimum
  • 0.5mm pitch: Usually requires 2+N+2
  • 0.4mm pitch: Likely needs 3+N+3 or any-layer

But pin count matters as much as pitch. A 100-pin 0.65mm BGA can often escape conventionally, while a 500-pin 0.8mm BGA might need HDI due to routing density.

Always try a conventional breakout first — before assuming HDI is necessary, verify you can't route your way out of it.


Originally published on the AtlasPCB Engineering Blog. We operate in-house CO2 and UV laser drill systems for HDI PCB fabrication — from 1+N+1 through 5+N+5, with stacked microvias and via-in-pad planarization.

Top comments (0)