Every multilayer PCB begins its life as a stackup drawing. Before a single sheet of copper laminate is cut, before the first drill bit spins, and long before your board reaches a reflow oven, the stackup drawing establishes the physical architecture of your circuit board. It defines how many copper layers exist, what separates them, how thick each dielectric is, what impedance targets must be met, and what the finished board thickness will be. Despite its importance, the stackup drawing is one of the most frequently misread documents in the PCB design-to-manufacturing workflow.
At AtlasPCB, our process engineers review hundreds of stackup proposals every month. We see the same misunderstandings repeated across projects — designers who confuse core with prepreg, engineers who approve a stackup without checking whether the proposed Dk values match their simulation frequency, and project managers who do not realize that an asymmetric construction will cause their boards to warp during assembly. This guide walks through every element of a PCB stackup drawing so that you can read, interpret, and confidently approve or challenge the proposal your manufacturer sends you.
Reviewed by AtlasPCB Engineering Team
Why You Need to Understand Your Stackup Proposal
In the standard PCB manufacturing workflow, the designer sends Gerber files, a drill file, and a fabrication drawing to the manufacturer. The manufacturer's process engineering team then proposes a stackup based on the designer's layer count, impedance requirements, material specification, and overall thickness target. This proposal comes back as a stackup drawing — typically a PDF or embedded table — that the designer must review and approve before fabrication begins.
This review step is not a formality. The stackup proposal is the single most consequential document in your design package because it determines whether your impedance targets are physically achievable, whether your board will survive thermal cycling, and whether your finished product fits its enclosure. A stackup that looks reasonable at first glance can contain subtle issues that lead to impedance failures in production, unexpected cost increases due to exotic material combinations, or delivery delays when a proposed prepreg style turns out to be on extended lead time.
The problem is that many designers treat stackup approval as a checkbox rather than an engineering review. They receive the proposal, see that the layer count and total thickness look correct, and reply with an approval. Weeks later, when impedance test coupons fail or boards arrive warped, the root cause traces back to a stackup detail that was visible in the drawing but never questioned. Understanding how to read a PCB stackup drawing transforms you from a passive approver into an active participant in your board's manufacturability. If you are still deciding between four-layer and six-layer constructions, getting comfortable with stackup drawings is an essential prerequisite.
Anatomy of a PCB Stackup Drawing — What Every Line Means
A PCB stackup drawing is a cross-sectional diagram of your board, drawn from top to bottom. Each horizontal line or band represents either a copper layer or a dielectric layer, and annotations alongside each element provide the specifications that govern fabrication. While formats vary between manufacturers, every stackup drawing contains the same fundamental information.
Layer designations appear as labels on the left side of the drawing, numbered sequentially from L1 (the top copper layer) through Ln (the bottom copper layer). A standard eight-layer board will show L1 through L8, with L1 at the top and L8 at the bottom. Some manufacturers use additional naming conventions — labeling layers as "TOP," "GND1," "SIG2," "PWR," "BOT" — to indicate function. These function labels tell you whether each copper layer is intended to carry signals, serve as a ground reference plane, distribute power, or perform a mixed role. Pay attention to these labels because they affect impedance modeling: a signal layer referenced to a solid ground plane behaves differently than one referenced to a split power plane with multiple voltage islands.
Material callouts identify what fills the space between copper layers. Every dielectric region is labeled as either a core or a prepreg, and most drawings include the specific laminate grade — such as FR-4 Tg170, Megtron 6, or IS415 — along with the prepreg style number when applicable. Understanding the difference between prepreg and core is fundamental to reading any stackup drawing, and the next section examines this distinction in detail.
Dielectric thickness is specified in mils or millimeters for each core and prepreg layer, often accompanied by a tolerance range. A typical entry might read "4.5 mil +/- 0.5 mil" for a prepreg layer or "8.0 mil +/- 0.3 mil" for a core. These thicknesses directly determine your impedance values, so even small discrepancies between what the manufacturer proposes and what your field solver assumed will shift your impedance results.
Copper weight is expressed in ounces per square foot, where 1 oz corresponds to approximately 1.4 mils (35 micrometers) of copper thickness. The stackup drawing may list both the base copper weight — the foil thickness before etching — and the finished copper weight after plating. Outer layers typically gain copper during the plating process, so an outer layer that starts as 0.5 oz base copper may finish at approximately 1.0 to 1.2 oz after pattern plating and surface finish. Inner layers remain at their base copper weight since they are etched before lamination and receive no additional plating.
Overall board thickness is stated at the bottom or side of the drawing, usually with a tolerance such as "1.6 mm +/- 10%." This figure includes all copper layers, all dielectric layers, the solder mask on both sides, and the surface finish. Verify that this number matches your mechanical enclosure requirements and connector specifications — a board that comes in at 1.75 mm when your card guide tolerates only 1.7 mm maximum will cause mechanical interference that cannot be corrected after fabrication.
Impedance targets may appear within the stackup drawing itself or in a separate impedance table attached to the same document. They specify the target impedance in ohms, the trace width and spacing required to achieve it, and the reference layer used as the return path. Impedance tables deserve their own discussion, which follows in a later section.
Drill span callouts appear on stackup drawings for boards with blind or buried vias. These annotations show which layers a via connects — for example, "L1-L4 blind via" or "L3-L6 buried via" — and they define the lamination sequence. A board with buried vias requires multiple press cycles, which affects both cost and lead time. If you see drill span callouts on your stackup proposal that you did not request, ask your manufacturer whether they are interpreting your via structure correctly.
Core vs Prepreg — Understanding the Building Blocks
The distinction between core and prepreg is the foundation of stackup literacy, yet it remains one of the most common sources of confusion among designers reviewing a stackup proposal for the first time.
A core is a fully cured, rigid laminate sheet that arrives at the factory with copper foil already bonded to one or both sides. Think of it as a finished, stable building block. The factory etches circuit patterns onto the core's copper surfaces, inspects the results with automated optical inspection, and then stacks the etched cores together with prepreg sheets between them. Because the core is already cured, its thickness is fixed and tightly controlled. When a stackup drawing shows a core at 8.0 mils, you can expect the actual thickness to fall within a narrow tolerance window — typically plus or minus 0.3 mils for thin cores and plus or minus 10 percent for thicker ones.
Prepreg, short for pre-impregnated, is a sheet of woven fiberglass cloth coated with partially cured (B-stage) epoxy resin. During the lamination press cycle, heat and pressure cause the resin to flow, filling the gaps left by etched copper patterns on adjacent layers and bonding everything together into a solid structure. Because the resin flows during pressing, the finished thickness of a prepreg layer depends on how much copper was removed from the adjacent layers. An inner layer with large copper pours leaves less space for resin to fill, so the prepreg finishes closer to its nominal thickness. An inner layer with minimal copper (mostly etched away) creates more void space, and the prepreg resin flows into those voids, making the finished prepreg layer thinner than its nominal specification.
On a stackup drawing, cores and prepregs are visually and textually distinct. Cores are typically shown as solid bands labeled with "Core" and a thickness, while prepregs are shown with a crosshatch or different shading and labeled with the prepreg style number. Common prepreg styles include 1080 (thin, approximately 2.8 mils nominal), 2116 (medium, approximately 4.6 mils nominal), and 7628 (thick, approximately 7.0 mils nominal). Manufacturers choose specific prepreg styles based on the dielectric thickness required for impedance control. When a stackup calls for a 5.0-mil dielectric, the process engineer might select a single sheet of 2116 plus resin content adjustment, or two sheets of 1080 stacked together. Multiple prepreg sheets give more precise thickness control and better resin fill for layers with heavy copper removal.
Another detail worth noting is the distinction between foil construction and cap construction on the outer layers. In foil construction, the outer copper is a thin foil sheet that is laminated directly onto prepreg during the final press cycle. In cap (or core) construction, the outer layers use a thin core with copper on both sides, where the inner copper surface is etched and the outer copper surface becomes the finished outer layer. Cap construction gives tighter thickness control on the outermost dielectric, which is critical for controlled impedance on outer-layer traces. If your design requires tight impedance tolerance on L1 or Ln, check whether your manufacturer's proposal uses foil or cap construction and understand the tradeoff.
Reading Impedance Tables in Your Stackup Proposal
For any design with controlled impedance requirements, the stackup drawing will include an impedance table — either embedded in the drawing itself or delivered as a companion document. This table is where your electrical intent meets your manufacturer's physical implementation, and it demands careful review.
A typical impedance table contains columns for impedance type (single-ended or differential), target impedance value in ohms, trace width, trace spacing (for differential pairs), copper layer, reference layer, dielectric thickness to the reference, and the Dk (dielectric constant) value used in the calculation. Some manufacturers also include their calculated impedance result and the tolerance window, typically plus or minus 10 percent.
Start your review by confirming that every impedance-controlled net class in your design appears in the table. If your design has 50-ohm single-ended traces, 90-ohm differential USB pairs, and 100-ohm differential Ethernet pairs, all three should be listed. Missing entries mean the manufacturer did not model those impedance targets, and the resulting trace geometry may not achieve your required values.
Next, check the trace widths against your design rules. The manufacturer's impedance model may require trace widths that differ from what you assumed during layout. A stackup with a thinner dielectric than you expected will require narrower traces to maintain the same impedance, and if those narrower traces violate your minimum width design rules, you have a conflict that must be resolved before fabrication.
The Dk value listed in the impedance table deserves particular scrutiny. Laminate datasheets typically report Dk at 1 MHz, but the effective Dk at your operating frequency can be significantly different. For standard FR-4 at 1 GHz, the Dk drops from the datasheet value of approximately 4.2-4.5 down to roughly 4.0-4.2. At 10 GHz, the effective Dk for high-speed laminates like Megtron 6 is around 3.6 versus a 1-MHz datasheet value of 3.7. If your manufacturer used the 1-MHz Dk value in their impedance calculation while you simulated at your actual operating frequency, the predicted impedance values will diverge. Ask which frequency their Dk value corresponds to, and if they cannot answer, that is a warning sign about the rigor of their impedance modeling.
Finally, verify the reference layer assignments. A signal trace on L3 referenced to a solid ground plane on L2 will have a different impedance than the same trace referenced to a power plane on L4, even if the dielectric thicknesses are identical, because copper pattern density on the reference layer affects the effective dielectric environment. For impedance-controlled designs, confirming the correct reference layer is non-negotiable.
Five Things to Check Before Approving a Stackup Proposal
After you understand every element on the drawing, a structured review ensures nothing critical slips through. These five checks, performed in order, will catch the vast majority of stackup issues before they become production problems.
First, verify that dielectric thicknesses support your impedance targets. Take the proposed dielectric thickness between each signal layer and its reference plane, plug it into your own field solver along with the manufacturer's proposed trace width and the correct Dk value at your operating frequency, and confirm that the calculated impedance falls within your tolerance window. Do not rely solely on the manufacturer's calculation — they may have used different Dk values, different copper roughness assumptions, or different solver software. Independent verification takes fifteen minutes and can prevent weeks of delay when impedance coupons fail.
Second, confirm that copper weights meet your current-carrying requirements. A stackup proposing 0.5 oz copper on inner power layers may not support the current density your power distribution network requires. Calculate the maximum current each power plane must carry, determine the required trace or plane cross-section using IPC-2152 guidelines, and verify that the proposed copper weight provides adequate margin. Outer layers are less of a concern because plating adds copper, but inner layers get exactly what the stackup specifies.
Third, check that the overall board thickness fits your mechanical constraints. Add up all the layers yourself — every copper thickness, every dielectric thickness, solder mask on both sides (typically 0.5 to 1.0 mil per side), and surface finish (ENIG adds about 0.2 mils, HASL adds more variability). Compare your total to the manufacturer's stated overall thickness. If the numbers do not match, one of you has an error. Also verify that the finished thickness, including tolerances, falls within your enclosure and connector specifications.
Fourth, ensure the proposed material grade matches your thermal and electrical requirements. If your design specifies Megtron 6 for low-loss high-speed signaling, but the stackup proposal shows standard FR-4 Tg170, you have a material mismatch that will cause signal integrity problems. Conversely, if your design only needs standard FR-4 but the manufacturer proposed a specialty laminate, you may be paying a premium without benefit. Check that the laminate grade, Tg rating, and Dk/Df characteristics align with your design intent.
Fifth, confirm that the stackup is symmetrical about the board center. A balanced stackup — where material types, dielectric thicknesses, and copper weights are mirrored around the midplane — prevents warpage during lamination and reflow. Compare the top half of the stackup to the bottom half layer by layer. If L1 has 1 oz copper on a 4-mil prepreg over a ground plane, then the corresponding bottom construction should mirror that arrangement. Asymmetric stackups create differential stress that causes boards to bow and twist, which leads to solder joint failures on fine-pitch BGAs and QFNs. If the proposed stackup is asymmetric, ask the manufacturer for the engineering justification and understand the warpage risk before approving.
When to Push Back on Your Manufacturer's Proposal
Not every stackup proposal deserves an immediate approval. There are specific situations where you should send the proposal back with questions or requested changes, and recognizing these situations is a skill that improves with experience.
The most common reason to push back is a material mismatch. If your fabrication notes specify a particular laminate system — say Isola 370HR for its combination of thermal performance and controlled Dk — and the manufacturer's proposal substitutes a different material without explanation, you need to understand why. Sometimes the substitution is benign: the factory may not stock your specified laminate but offers an equivalent from a different supplier with matching Dk, Df, Tg, and CTE characteristics. Other times, the substitution changes the electrical performance of your board in ways the manufacturer may not have evaluated. Ask for the datasheet of the proposed alternative, compare the key parameters at your operating frequency, and make an informed decision rather than accepting a material change on faith.
Impedance target discrepancies are another trigger for pushback. If the impedance values in the manufacturer's table differ from your design intent by more than the agreed tolerance, the stackup needs revision. This can happen when the manufacturer uses a different stackup arrangement than you assumed in layout — for example, referencing a signal layer to a power plane instead of a ground plane, or using a thinner dielectric that requires trace width changes you have not accounted for in your layout. Resolve these discrepancies before approving rather than hoping the impedance will fall within tolerance during production.
Asymmetric stackups without justification should always prompt a conversation. While there are legitimate reasons for asymmetry — some rigid-flex designs and certain via-in-pad constructions require it — a manufacturer should be able to explain why the proposed stackup is not balanced. If the answer is simply "this is what our standard book stackup looks like," push for a modification that achieves symmetry. The small increase in material cost is almost always cheaper than dealing with warped boards on your assembly line.
Non-standard prepreg combinations that may affect availability are worth questioning as well. If the stackup calls for an unusual combination of prepreg styles — for example, three sheets of 1080 where a single sheet of 2116 plus one 1080 would achieve the same thickness — ask whether the proposed combination offers a tangible benefit or is simply how the software generated the solution. Simpler prepreg combinations mean fewer material line items to procure, which can reduce lead time and price.
Finally, look for cost optimization opportunities the manufacturer may not have suggested. A stackup that uses 2 oz copper on all inner layers when only one power layer actually needs heavy copper is more expensive than it needs to be. A construction that requires three lamination press cycles when a minor rearrangement of blind via spans could reduce it to two will save both time and money. Manufacturers are often conservative in their proposals because the safest stackup for fabrication yield is not always the most cost-effective stackup for you. If you understand the drawing well enough to identify these opportunities, you can negotiate a better balance of performance, reliability, and cost.
Stackup Review Workflow — From Proposal to Production
Integrating stackup review into your project schedule requires treating it as an engineering milestone rather than an administrative step. The most effective workflow follows a clear sequence from initial proposal through final approval, with specific checkpoints that prevent schedule surprises.
The process begins when you submit your fabrication package and the manufacturer returns a stackup proposal. Set a firm internal deadline for completing your review — typically two to three business days. During this window, perform the five-point check described above, run your own impedance simulations against the proposed geometry, and compare the material specification to your design requirements. If the proposal passes all checks, approve it and note the approval date in your project tracker. If it does not, send back specific, actionable feedback rather than vague concerns. "The dielectric between L3 and L4 should be 4.0 mils, not 3.5 mils, to maintain 50-ohm impedance at 5/3.5 trace width/spacing" is far more productive than "please check the impedance."
Once you approve the stackup, you have reached what the industry calls "stackup freeze." After this point, changes to the stackup require a formal revision cycle with a new proposal, new impedance calculations, and potentially new layout adjustments. Stackup changes after freeze are the single most common source of schedule delay in multilayer PCB projects, because every change ripples through impedance modeling, trace width adjustments, design rule checks, and Gerber regeneration. Build adequate time into your project schedule for the initial review so that you get it right the first time, rather than rushing an approval and discovering problems after fabrication has started.
For complex projects with 12 or more layers, hybrid material stackups, or blind and buried vias, consider requesting a pre-production stackup review meeting — a 30-minute call with the manufacturer's process engineer to walk through the proposal line by line. This investment of time pays for itself many times over by catching ambiguities in the drawing, aligning expectations on tolerance and process capability, and building a working relationship with the person who will ultimately oversee your board's fabrication.
The stackup drawing is not just a technical specification — it is the contract between your design intent and the manufacturer's fabrication process. Every line on that drawing translates directly into a physical reality inside your finished PCB. Learning to read it with the same rigor you apply to your schematic review will make you a better designer, a more effective manufacturing partner, and a more confident owner of the boards that carry your designs into production.
Originally published on AtlasPCB Engineering Blog. We manufacture advanced multilayer PCBs with full impedance simulation and stackup optimization for high-speed, RF, and HDI applications.
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