How to Specify Impedance Control in Your PCB Fab Drawing: The 5 Elements That Prevent Failure

How to Specify Impedance Control in Your PCB Fab Drawing

The most common cause of impedance failure is not manufacturing error — it's incomplete specification. Having reviewed approximately 400 impedance-controlled designs per month in our facility, roughly 30% arrive with specifications that cannot be fabricated as drawn without clarification.

The engineer's simulation was correct. The information transferred to the manufacturer was not.

The 5 Elements Every Impedance-Controlled Fab Drawing Needs

1. Impedance Table — Net class, target Zo (ohms), tolerance, trace width, spacing (differential), signal layer, reference plane(s)
2. Target Stackup — Layer-by-layer dielectric thickness, copper weight, material specification
3. Dk Value with Frequency — The dielectric constant used in simulation, at what frequency
4. Measurement Standard — "Per IPC-TM-650 2.5.5.7" (TDR method on coupon)
5. Width Adjustment Permission — Whether the fab may modify trace width to achieve impedance targets

Missing any single one forces the manufacturer to make assumptions that may not match your simulation.

Why the Dk Value Matters More Than You Think

Impedance is an emergent property of trace geometry, dielectric thickness, dielectric constant, copper roughness, and solder mask thickness. Your simulation tool accounts for all these internally. But when you write "50 ohm +/-10%" without specifying which Dk you assumed, the manufacturer must reverse-engineer your intent.

Consider a 50-ohm microstrip on Layer 1 of a 6-layer board. If your simulation assumed Dk = 4.2 for generic FR-4 but the manufacturer uses Isola 370HR (Dk = 4.04 at your frequency), the impedance will be 3-4 ohms higher than your target — potentially outside tolerance before any manufacturing variation is considered.

When customers provide complete stackup with Dk callout, we achieve first-pass impedance yield above 95%. Without Dk specification, first-pass yield drops to approximately 82% — necessitating trace width iteration that adds 2-3 days.

The 7 Most Common Impedance Specification Mistakes

Based on ~4,800 impedance-controlled designs processed in the past year:

1. No Dk value specified (38% of designs)
Engineer simulated with Polar's default "generic FR-4" Dk of 4.2, actual material has Dk = 4.04 at operating frequency. Result: 3-5% systematic impedance offset.

2. Reference plane not explicitly stated (24%)
Inner-layer stripline where one adjacent layer is actually a split power plane with gaps under signal traces. Impedance in those regions is 8-12% higher than target.

3. Differential impedance stated without single-ended target (18%)
"100 ohm differential" can mean different things depending on coupling. If loosely coupled (space > 3x width), Zdiff ≈ 2x Zse. If tightly coupled (space = width), each line might be 60 ohm with Zdiff = 100 ohm. Manufacturer needs both values.

4. Missing width adjustment note (15%)
Traces drawn at exactly 4.0 mil from simulation, but actual prepreg thickness is 4.2 mil (within laminate tolerance), making impedance 2 ohms high. Without permission to adjust to 4.3 mil width, the fab must ship out-of-spec or call for deviation.

5. Solder mask effect ignored (12%)
Solder mask adds 2-3 mil of dielectric over outer-layer microstrip, lowering impedance by 2-5%. For +/-10% tolerance this is fine; for +/-5% it's the difference between pass and fail.

6. Mixed tolerance on a single layer (8%)
"USB3 = 90 ohm +/-10%, PCIe Gen5 = 85 ohm +/-5%" on the same layer creates manufacturing conflict. Width adjustment for the tight-tolerance net affects the relaxed-tolerance net through etch compensation.

7. Impedance on non-length-matched pairs (5%)
Controlled differential pairs with 200+ mil intra-pair skew. Impedance control is pointless without matching — skew creates common-mode conversion that no impedance accuracy can compensate.

Tolerance Selection: Cost vs. Requirement

Impedance tolerance directly drives board cost:

Tolerance	Cost Impact	First-Pass Yield	Appropriate For
+/-10%	No premium	>95%	USB, DDR3/4, HDMI, PCIe Gen 1-4, 1G/10G Ethernet
+/-7%	+5-10% cost	~90%	PCIe Gen 5/6, 25G+ SerDes, DDR5, USB4
+/-5%	+15-25% cost	~80%	56G PAM4, mmWave RF, automotive radar
+/-3%	+40-60% cost	~65%	Metrology-grade RF, satellite transponder filters

The engineering question: what tolerance does your link budget actually need? If your SI simulation shows 3 dB margin at 10% variation, specifying 5% wastes money. We see this frequently — engineers specify +/-5% "to be safe" when +/-10% is functionally adequate, adding 20% to cost with no benefit.

What Your Impedance Table Must Contain

Every column matters:

• Net Class / Signal Group: Group by impedance requirement, not individual net name
• Impedance Type: Single-ended (microstrip/stripline), differential (edge-coupled), or coplanar (GCPW)
• Target Impedance: For differential pairs, state BOTH single-ended and differential: "Zdiff = 90 ohm (Zse = 45 ohm/line), +/-10%"
• Trace Width / Spacing: Include simulated values as starting point with note: "Manufacturer may adjust +/-0.5 mil"
• Signal Layer: Which layer(s) — different layers need different trace widths for same impedance
• Reference Plane(s): For stripline, BOTH references: "L4 referenced to L3 (GND) and L5 (GND)"

Stackup Specification Done Right

A proper stackup for impedance-controlled boards includes:

• Layer-by-layer construction with thickness to 0.1 mil resolution: "Prepreg L1-L2: 4.0 mil (1x 1080 glass style, 65% resin content)"
• Specific material: "Isola 370HR" — not just "FR-4" (which has Dk ranging 3.8 to 4.8 across manufacturers)
• Dk at frequency: "Dk = 4.04 at 10 GHz (per Isola 370HR datasheet, IPC-TM-650 2.5.5.5)"
• Copper weight: State finished copper weight (after plating for outer layers — 1 oz base becomes ~1.7 oz after plating)

Measurement and Verification

When you specify impedance control, the manufacturer adds test coupons to production panels — small trace structures replicating your controlled net geometries in the panel border. These are measured with TDR per IPC-TM-650 2.5.5.7 after fabrication.

Your impedance test report should include: coupon identification, measurement equipment and calibration date, raw TDR traces or tabulated values, pass/fail determination, and actual measured impedance for each net class.

Important nuance: coupon measurements represent AVERAGE impedance over trace length. They don't capture local discontinuities from via transitions, pad entries, or reference plane gaps. The coupon confirms the manufacturer achieved correct geometry and dielectric build — not that your routing decisions are sound.

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Based on production data from 4,800+ impedance-controlled designs processed in our facility.

Further Reading:

• PCB Stackup Design Guide: Layer Assignment for Mixed-Signal — How to assign signal layers and reference planes
• RF PCB DFM Rules for High-Frequency Boards — DFM considerations specific to RF designs
• HDI PCB Cost Breakdown: Microvia Layer Pricing — Understanding HDI cost drivers

Working on an impedance-controlled design? AtlasPCB provides TDR measurement reports with every impedance-controlled order, up to 30 layers, all materials including FR-4, Rogers, and Megtron.