The 30-Second Decision
| Your Fastest Signal | Standard ±10% | Tight ±5% | Notes |
|---|---|---|---|
| SPI/I2C (<100 MHz) | Sufficient | Overkill | Save the cost |
| USB 2.0 (480 Mbps) | Sufficient | Optional | Only if trace >6" |
| Gigabit Ethernet | Acceptable | Recommended | Depends on connector quality |
| USB 3.2 Gen 2 (10G) | Marginal | Required | Return loss will fail |
| PCIe Gen 4 (16 GT/s) | Fails | Required | Plus low-loss dielectric |
| PCIe Gen 5 (32 GT/s) | Fails | Minimum | Need ±3% or better |
| 25G/56G Ethernet | Fails | Tight minimum | Material Dk tolerance matters too |
If your fastest interface is below the bold line — standard fabrication works. Above it, you need an impedance-controlled PCB manufacturer with TDR verification capability.
What Creates the Tolerance Difference
The impedance of a PCB trace depends on four physical parameters: trace width, dielectric thickness, dielectric constant (Dk), and copper thickness. Manufacturing variation in any of these affects final impedance.
Standard fabrication uses catalog Dk values for impedance calculation, applies a generic etch factor, and presses the laminate at standard parameters. Each parameter varies within its natural process window, and those variations compound multiplicatively.
In production data, standard-process boards show impedance distribution with a standard deviation of approximately 3.5% — meaning ±10% captures the 3-sigma range. This is perfectly acceptable for the majority of PCB applications.
Tight tolerance production starts differently. Before fabrication begins, the process engineering team simulates the stackup using measured Dk data from the actual material lot. Rogers publishes Dk to two decimal places, but actual pressed values vary by ±0.03 between lots — at 10 GHz, this alone creates 1-2% impedance variation. By measuring the specific material, this variable is eliminated.
The Etch Compensation Problem
Etch compensation is where most impedance failures originate. When copper is etched, the chemical process removes material laterally as well as vertically. A trace designed at 5.0mil will etch to approximately 4.2-4.5mil depending on copper weight, resist type, and chemistry freshness.
Standard shops apply a fixed etch compensation: typically +0.5mil for 0.5oz copper, +1.0mil for 1oz, +1.5mil for 2oz. This generic approach works within ±10%.
A controlled-impedance manufacturer characterizes their actual etch bias weekly, broken down by copper weight, panel position (edges etch more than centers), and bath chemistry age. The difference between a fresh chemistry bath and one approaching change-out can shift etch bias by 0.3mil — enough to move impedance by 3-4% on fine traces.
For tight impedance control, artwork is compensated differently based on trace position relative to panel edges — something no standard shop does because it requires custom CAM engineering for each job.
When to Specify — And When Not To
Over-specifying impedance control wastes money. Under-specifying causes signal integrity failures.
Consider a typical IoT device with a STM32, SPI flash, I2C sensors, and a WiFi module. Only the RF trace to the antenna needs impedance control. Specifying control on the entire board adds 20% to cost with zero benefit.
Conversely, a network switch PCB with 10G SerDes, DDR4, and PCIe Gen 4 needs tight impedance control on virtually every signal layer.
Practical guideline: If your design simulation shows less than 1 dB return loss margin at your operating frequency with ±5% impedance, you need controlled impedance. If your simulation shows 3+ dB margin with ±10%, standard fabrication saves cost without risk.
How to Specify Impedance in Your Fab Drawing
Effective impedance specification requires four elements that many designers omit:
1. Target impedance and tolerance for each controlled net class. Don't simply write "50 ohm ±10%." Specify: "Differential 100 ohm ±5% for USB 3.2 pairs on Layers 1/8, Single-ended 50 ohm ±7% for RGMII traces on Layer 3."
2. Reference plane identification. Impedance depends on distance to the reference ground plane. A common failure: the designer assumes Layer 3 references Layer 2 (ground), but the manufacturer interprets it as referencing Layer 4 (power).
3. Stackup constraints. If your design assumes specific dielectric thickness, state this explicitly. Manufacturers will adjust dielectric thickness to optimize panel cost unless constrained.
4. Copper roughness specification. At frequencies above 5 GHz, copper surface roughness affects both impedance and loss. If your simulation assumes specific roughness, specify it.
Cost Optimization: Getting Tight Tolerance Where It Matters
The most cost-effective approach for mixed-signal designs is selective impedance control:
- Identify which layers carry speed-critical signals — specify ±5% only on those layers
- For a typical 8-layer board, you might only need impedance control on 4 of 8 layers
- Consider hybrid stackups where low-loss materials serve high-speed layers and standard FR-4 handles power/low-speed
- Distinguish between nets needing ±5% versus those where ±7% suffices
Verification: What Your TDR Report Should Show
When you receive boards from an impedance-controlled PCB manufacturer, the TDR report should contain:
- Target impedance for each coupon (matched to your specification)
- Measured impedance with measurement uncertainty stated
- Pass/fail against your specified tolerance
- Coupon location on panel (identifies positional variation)
- Date, instrument model, and calibration status
If a manufacturer provides impedance "data" without coupon identification or instrument details, the numbers are likely calculated from process parameters rather than actually measured.
Key Takeaways
- Below 3 Gbps with short traces: standard ±10% tolerance is fine — save 15-30% on board cost
- Above 5 Gbps: tight ±5% tolerance is recommended to mandatory depending on trace length
- The cost difference is 15-30% — driven by simulation, calibration, and TDR verification
- Selective impedance control (only on layers that need it) optimizes cost
- Always specify reference planes and stackup constraints in your fab drawing
- Demand actual TDR data, not calculated impedance estimates
Originally published on AtlasPCB Engineering Blog. We manufacture impedance-controlled PCBs with ±5% TDR-verified tolerance — from standard FR-4 through Rogers and PTFE materials.
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