If you've ever gotten PCB boards back from fabrication and found your impedance 3-5 ohms off from what your simulator predicted, the most likely culprit isn't your dielectric constant assumption or your field solver settings — it's etch factor.
Every copper trace on a PCB starts wider than it ends up. The chemical etching process that forms conductors doesn't just dissolve copper downward through exposed areas — it also attacks laterally under the etch resist. This lateral undercut produces traces with a trapezoidal cross-section rather than the ideal rectangle your EDA tool draws.
The ratio between etch depth (copper thickness) and lateral undercut is the etch factor. Understanding it — and specifying your designs accordingly — is the difference between first-pass impedance success and costly respins.
The Math That Matters
The etch factor (EF) is defined as:
EF = D / U
Where D is etch depth (= copper thickness) and U is lateral undercut per side. A higher number means less undercut — always better.
For a trace with resist width W_resist, the finished base width is:
W_base = W_resist - 2(D/EF)
The effective electrical width (what determines impedance) is the average of top and base:
W_effective = (W_top + W_base) / 2
This is why rectangular-profile impedance models give optimistic results. The narrower base increases actual impedance above the rectangular prediction.
Real-World Etch Factor by Copper Weight
From our production data running impedance-controlled panels on horizontal conveyorized spray-etch equipment:
| Copper Weight | Thickness | Typical EF Range | Undercut per Side | Total Width Loss |
|---|---|---|---|---|
| 0.5 oz | 17.5 μm | 3.0 - 4.0 | 4.4 - 5.8 μm | 0.35 - 0.46 mil |
| 1 oz | 35 μm | 2.5 - 3.5 | 10 - 14 μm | 0.79 - 1.10 mil |
| 2 oz | 70 μm | 2.0 - 3.0 | 23 - 35 μm | 1.81 - 2.76 mil |
| 3 oz | 105 μm | 1.8 - 2.5 | 42 - 58 μm | 3.31 - 4.57 mil |
The key insight: 1-oz copper loses approximately 1 mil of total trace width. For a 5-mil target trace, that's a 20% width reduction — enough to shift 50-ohm impedance by 4-6 ohms.
How Fabricators Compensate
When your PCB fabricator receives impedance-controlled design data, their CAM team applies etch compensation — bloating trace features outward to account for the expected undercut.
The compensation formula works backward:
W_resist = W_target + 2(D/EF)
A 5-mil target on 1-oz copper with EF = 3.0 gets approximately 0.46 mil per side added, producing an artwork width of ~5.9 mil. After etching removes ~0.9 mil total, you end up at your target.
Good fabricators don't just use theoretical calculations — they maintain empirical compensation tables from production SPC data, updated as equipment ages and chemistry drifts. At AtlasPCB, we track etch factor on every impedance-controlled production lot using cross-section analysis, feeding measurement data back into our CAM compensation values.
Why Your Impedance Drifts Between Fab Shops
When you move a design from one fabricator to another and impedance shifts, etch factor is usually the explanation. Each facility has different:
- Etchant chemistry (cupric chloride vs. ammoniacal)
- Equipment configuration (spray pressure, nozzle oscillation)
- Process monitoring frequency
- Compensation table methodology
A fabricator achieving EF = 3.2 on 1-oz copper will apply different compensation than one achieving EF = 2.8. If you move your design without discussing the new facility's process capability, the impedance shift is inevitable.
Design Guidelines for Better Etch Results
Match copper weight to feature size. A practical minimum trace width is 3x the copper thickness. For 1-oz copper (35 μm), that's about 4.1 mil minimum — exactly where most fabricators set their standard capability limit.
Model trapezoidal geometry. Modern field solvers (Polar Si9000, Ansys 2D Extractor) handle trapezoidal conductors natively. Use an etch factor of 3.0 for 1-oz copper as your starting assumption — then ask your fabricator for their actual data.
Specify clearly in fab notes. Include: target impedance with tolerance, whether the width spec refers to top, base, or average, and the reference stackup with dielectric constants.
Don't ignore copper weight changes from plating. Outer layers start at 1 oz but finish at 1.2-1.4 oz after panel and pattern plating. That extra copper means more etch time and more undercut than the base weight suggests.
The Differential Pair Problem
Etch factor affects differential pairs doubly. Both trace widths narrow (changing single-ended impedance) AND the gap between traces widens (reducing coupling). A designed 5-mil gap becomes effectively 5.9 mil after etching on 1-oz copper — reducing coupling by enough to push differential impedance 3-5 ohms above target.
This is why experienced high-speed designers specify gap requirements as post-etch minimums, not artwork dimensions. The fabricator then knows to verify that the widened post-etch gap still meets the coupling requirement.
What to Ask Your Fabricator
Before committing your impedance-controlled design to production, get answers to these:
- What etch factor do you typically achieve on [your copper weight]?
- Do you compensate inner and outer layers differently?
- What's your etch factor variation (within-panel and lot-to-lot)?
- Do you use trapezoidal or rectangular profiles in your impedance modeling?
These conversations happen during the stackup review phase — ideally before you start layout, not after boards come back wrong.
This article is based on production etch data from impedance-controlled multilayer fabrication. Originally published at AtlasPCB Engineering Blog.
Our process engineers review etch compensation for every impedance-controlled design we manufacture. If you're working on a design where etch factor matters, our DFM team can share specific process capability data for your copper weight and feature sizes.
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