PCB Stackup Design Guide: Layer Assignment, Impedance Planning, and DFM Rules
Getting your PCB stackup right before ordering is the single highest-impact decision for signal integrity, EMI performance, and first-pass manufacturing success. This guide covers the practical engineering decisions for 4-16 layer boards.
The 30-Second Stackup Decision
| Layer Count | Recommended Assignment | Best For |
|---|---|---|
| 4-layer | SIG-GND-PWR-SIG | Simple mixed-signal, cost-optimized |
| 6-layer | SIG-GND-SIG-PWR-GND-SIG | USB3/PCIe Gen3, moderate density |
| 8-layer | SIG-GND-SIG-GND-PWR-SIG-GND-SIG | DDR4/5, PCIe Gen4+ |
| 10-layer | SIG-GND-SIG-GND-PWR-GND-SIG-GND-SIG-SIG | High-density BGA breakout |
| 12-16 layer | Follow 60/40 rule: 60% reference planes | Server, networking, FPGA |
The single most important principle: every high-speed signal layer must have an adjacent, unbroken reference plane.
Layer Assignment: Foundation of Signal Integrity
The assignment of signal and reference plane layers determines impedance, crosstalk, and EMI behavior before you route a single trace.
For a standard 4-layer board: signal on L1, ground on L2, power on L3, signal on L4. This gives both signal layers an adjacent ground reference at controlled dielectric distance.
The common mistake: placing signals on L2 and L3 (inner layers) with ground/power on outside. While it seems logical for EMI containment, inner signal layers between planes at different potentials create unpredictable reference transitions.
For 6+ layers, maintain a reference plane adjacent to every signal layer. In our production data at AtlasPCB, boards following this rule achieve first-pass impedance compliance above 96%, compared to 78% for boards with non-standard assignments.
Prepreg and Core Selection: The Numbers That Matter
A stackup drawing is only as good as its material specifications. "FR-4" is a material class, not a single product — different prepreg styles have dramatically different pressed thicknesses.
Common Prepreg Styles (FR-4, Tg 170)
| Style | Nominal Thickness | Pressed Thickness | Resin Content |
|---|---|---|---|
| 1080 | 0.076mm (3.0mil) | 0.066-0.073mm | 65% |
| 2116 | 0.120mm (4.7mil) | 0.105-0.115mm | 52% |
| 7628 | 0.185mm (7.3mil) | 0.175-0.185mm | 42% |
The pressed thickness (after lamination) determines your impedance — not the nominal datasheet value.
Approximately 25% of first-time stackup submissions specify dielectric thicknesses that don't correspond to any available prepreg combination. For example, 3.5mil falls between 1x1080 (2.7mil) and 1x2116 (4.2mil) with no single-ply option available.
Practical process: Start with impedance target → calculate required trace width and dielectric → verify that the dielectric thickness matches available prepreg combinations → adjust trace width for nearest available material.
Impedance Planning: Getting to +/-5% First Pass
Achieving tight impedance tolerance means designing a stackup where manufacturing naturally produces the correct impedance.
What manufacturers control tightly:
- Trace width: +/-0.5mil (LDI exposure)
- Copper thickness: +/-3um
- Prepreg ply count: exact
What varies moderately:
- Pressed dielectric thickness: +/-8% across panel
- Resin fill around traces: depends on copper density
- Dk value: +/-3% between lots
Design your stackup to nominally produce 50.0 ohms at the center of all tolerance windows. Don't design to 47.5 ohms hoping everything lands on the low side.
For differential pairs, coupling between traces adds another variable. Design for 100-ohm differential with minimum 4mil gap to give adequate process margin.
Common DFM Violations We Catch
Based on DFM reviews we perform, these are the most frequent stackup issues:
1. Copper weight imbalance → warpage
A 10-layer board with 2oz on L1-5 and 0.5oz on L6-10 bows after lamination. Copper weight shouldn't differ by more than 1oz between top and bottom halves.
2. Insufficient dielectric for voltage withstand
IPC-2221B specifies minimum spacing based on voltage. A 48V power plane 3mil from an adjacent signal layer is below the 5mil minimum for 50V DC.
3. Asymmetric plane splits creating impedance discontinuities
Traces crossing ground plane splits lose their reference and radiate EMI. Add stitching vias along split boundaries.
4. Via aspect ratio exceeding plating capability
2.4mm thick board with 0.15mm holes = 16:1 aspect ratio at the limit of reliable plating. Via barrel may be thin at center.
Proven Stackup Templates
4-Layer Standard (General Digital)
- L1: Signal (1oz) — microstrip
- PP: 2x1080 (0.15mm)
- L2: GND (1oz)
- Core: 1.0mm
- L3: PWR (1oz)
- PP: 2x1080 (0.15mm)
- L4: Signal (1oz)
- Total: 1.6mm | 50-ohm: 5.2mil trace
8-Layer High-Speed (DDR4/5, PCIe Gen4)
- L1: Signal (1oz)
- PP: 1x2116 (0.105mm)
- L2: GND (0.5oz)
- Core: 0.2mm
- L3: Signal (1oz)
- PP: 2x1080 (0.15mm)
- L4: GND (0.5oz)
- Core: 0.4mm
- L5: PWR (0.5oz)
- PP: 2x1080 (0.15mm)
- L6: Signal (1oz)
- Core: 0.2mm
- L7: GND (0.5oz)
- PP: 1x2116 (0.105mm)
- L8: Signal (1oz)
- Total: 1.6mm | Stripline 50-ohm: 3.8mil trace
These configurations are production-proven with characterized impedance results from hundreds of panels.
Key Takeaways
- Every high-speed signal layer needs an adjacent unbroken ground plane
- Specify exact prepreg styles (1080/2116/7628), not just "FR-4"
- Verify your target dielectric thickness matches available material combinations
- Maintain symmetry around the board center to prevent warpage
- Plan impedance at the center of all tolerance windows, not the edge
Need stackup review before ordering? AtlasPCB engineers simulate your stackup against actual material inventory and confirm impedance targets are achievable — before production starts.
Further reading:
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