PCB Thermal Design for Edge AI Inference Accelerators
Edge AI inference is hitting a wall that has nothing to do with silicon — it's the PCB. When you pack 15-75W of AI compute into a compact, fanless enclosure, the board becomes your primary thermal management system. Unlike data center GPU boards with unlimited airflow, edge PCBs must conduct heat through the laminate itself.
Data Center vs Edge: The Thermal Gap
| Parameter | Data Center AI | Edge AI Inference |
|---|---|---|
| Power budget | 300-1000W | 15-75W |
| Cooling | Forced air (30-60 CFM) | Conduction + natural convection |
| Ambient | 25-35°C (controlled) | 0-55°C (uncontrolled) |
| Board size | 300×300mm+ | 80×120mm typical |
| Airflow | 2-5 m/s | 0-1 m/s (sealed) |
| Layers | 16-24 | 8-12 |
The Power Density Reality
Today's edge AI SoCs (Hailo-15, Jetson Orin NX, Qualcomm Cloud AI 100 Edge) pack 15-75W into thermal pads of 15×15mm to 35×35mm. That's 1.5-5.5 W/cm² of concentrated heat.
Standard FR-4 without thermal management reaches ~60°C rise per W/cm² in still air. At 3 W/cm² (a modest 45W SoC): 180°C rise — game over without proper board design.
The 10-Layer Sweet Spot
Across dozens of edge AI boards we've manufactured, 10 layers emerges as the optimal balance:
| Layer | Function | Cu Weight |
|---|---|---|
| L1 | Signal + Component | 1oz |
| L2 | Ground (reference) | 2oz |
| L3 | Signal (DDR5) | 1oz |
| L4 | Power (VDD_CORE) | 2oz |
| L5 | Ground (shield) | 2oz |
| L6 | Power (VDD_IO) | 2oz |
| L7 | Signal (low-speed) | 0.5oz |
| L8 | Ground (thermal) | 3oz |
| L9 | Signal + aux power | 1oz |
| L10 | Ground + thermal pad | 2oz |
Layer 8 at 3oz copper is specifically optimized for thermal spreading. At 105μm thickness, it has lateral thermal conductivity equivalent to a 0.4mm aluminum plate — embedded within the lamination with no assembly steps.
Thermal Via Array: The Numbers
The via array under the SoC is the single most impactful thermal feature:
- Coverage: Fill 80-90% of thermal pad area
- Drill: 0.3mm, copper-filled (IPC-4761 Type VII)
- Pitch: 1.0mm
- Result: ~360 vias under a 20×20mm pad
- Thermal resistance: 1.5-3.0°C/W for the via array (10-layer, 2-3oz)
Critical pitfall we catch in DFM review: Engineers place thermal vias but connect them to only some internal planes (thermal reliefs isolate others). A via connected to 3 of 8 copper layers has only 40% of the thermal capacity. Remove thermal reliefs on all thermal vias.
PDN Challenge: 90A at 0.8V
A 75W SoC at 0.8V draws ~93A peak. The entire PDN must maintain <25mV DC drop + <40mV AC ripple.
Design rules:
- VRM placement: Within 10-15mm of SoC power pins (non-negotiable)
- Power plane copper: 2-3oz minimum (1oz creates 8mV drop per square at 90A)
- Bulk decoupling: Adjacent to VRM output (100-470μF)
- Bypass caps: Within 2mm of each power BGA ball group (0.1-1μF)
Material Selection
Baseline: High-Tg FR-4 (Tg ≥170°C, Td ≥340°C). Copper planes near the SoC reach 90-100°C continuously — standard Tg-150 material degrades.
High-speed memory layers: If running LPDDR5X at 4-5 GHz data rate, consider Megtron 4 or I-Tera on signal layers for loss performance.
Design Checklist
Before releasing for fab:
- ☐ Material: High-Tg (170°C+) specified
- ☐ Copper weight per layer explicitly stated
- ☐ Thermal via array: drill, pitch, fill spec, plane connectivity
- ☐ Power plane min trace/space meets capability for chosen copper weight
- ☐ Controlled impedance for DDR/LPDDR5X layers
- ☐ Via-in-pad specified for SoC and VRM thermal pads
- ☐ Board thickness tolerance for TIM compression
Full article with thermal simulation data and detailed stackup tables: atlaspcb.com/blog/pcb-thermal-design-ai-edge-inference-accelerator-power-density
Designing edge AI hardware? We build 8-12 layer boards with mixed copper weights (1oz signal + 3oz power), filled thermal via arrays, and controlled impedance DDR5 interfaces — see our full HDI and heavy-copper capabilities.
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