Originally published on AtlasPCB Blog
Heat is the persistent adversary of power electronics reliability. Every watt dissipated by a power MOSFET, voltage regulator, or LED driver must find a path from the junction through the package, across the solder interface, through the PCB, and ultimately to the ambient environment or a heatsink. In this thermal chain, the PCB itself often represents the highest thermal resistance element, particularly when the heat-generating component is mounted on the top surface and the heatsink or cooling structure is attached to the bottom. Thermal via arrays, columns of plated vias that provide a direct copper path through the board thickness, are the primary mechanism for reducing the PCB's contribution to the overall thermal resistance.
The design of thermal via arrays involves far more subtlety than simply filling an exposed pad area with as many vias as will fit. The via diameter, pitch, plating treatment, fill method, and interaction with the copper planes all influence the effective thermal conductivity of the array. Furthermore, when thermal vias are placed within component pads, the via-in-pad construction requires specific planarization and capping processes that affect both assembly solderability and long-term reliability. In our fabrication process, thermal via arrays represent a frequent intersection of thermal engineering requirements with manufacturing process capabilities, and the solutions we implement must satisfy both domains simultaneously.
Thermal Conduction Through Via Arrays: Physics and Modeling
The thermal conductivity of bulk copper is approximately 385 W/m-K, making it an excellent conductor of heat. However, a thermal via is not a solid copper cylinder. A conventionally plated via consists of a thin copper tube, typically 20 to 35 micrometers wall thickness, surrounding a hollow core. The effective thermal conductivity of this hollow structure is dramatically lower than solid copper because the air or resin fill within the hollow core contributes negligible thermal conduction.
To calculate the effective thermal conductivity of a via array, one must consider the parallel thermal paths: the copper barrel walls, any fill material within the via, and the surrounding dielectric material between vias. The copper cross-sectional area for a conventionally plated via with a 0.3 mm drilled diameter and 0.025 mm copper plating is the annular ring area, calculated as pi times the drill radius squared minus pi times the inner radius squared. This yields approximately 0.0216 square millimeters of copper per via, compared to 0.0707 square millimeters for a solid copper cylinder of the same diameter. The copper area fraction, and therefore the thermal conduction capacity, of a hollow via is only about 30 percent of what a solid copper plug would provide.
This analysis reveals why via fill and copper fill technologies exist. By filling the via core with thermally conductive material, whether copper, silver-filled epoxy, or conductive paste, the effective thermal cross-section can be substantially increased. Solid copper fill, achieved through specialized electroplating processes that deposit copper from the bottom of the via upward until the via is completely filled, provides the maximum possible thermal performance because the entire via cross-section becomes copper. However, copper-filled vias require significantly longer plating cycles and specialized chemistry, making them more expensive than conventional plated vias.
In our thermal modeling work for customer designs, we calculate the effective thermal resistance of a via array using a parallel resistance network model. Each via contributes a thermal resistance equal to its length divided by the product of its effective thermal conductivity and its cross-sectional area. The vias in the array operate in parallel, so the total array thermal resistance is the individual via resistance divided by the number of vias. The surrounding FR4 dielectric, with a thermal conductivity of only 0.25 to 0.30 W/m-K, contributes a parallel thermal path that is typically negligible compared to the via array contribution but is included for completeness.
Via Diameter, Pitch, and Array Density Optimization
The selection of via diameter and pitch for a thermal array involves balancing thermal performance against manufacturing feasibility and electrical design constraints. A larger via diameter provides more copper cross-section per via, improving thermal conduction. However, larger vias consume more pad area and require larger anti-pads on internal power and ground planes, potentially disrupting current distribution or creating impedance discontinuities for nearby signal traces.
A common thermal via specification for power electronics applications uses 0.3 mm drilled diameter with a pitch of 0.8 to 1.0 mm center-to-center. This geometry provides a reasonable via density within a typical thermal pad area while maintaining adequate copper between vias on the surface layer for solder attach. For a thermal pad measuring 5 mm by 5 mm, a grid of vias at 1.0 mm pitch provides 25 vias within the pad area. If these are conventionally plated with 25 micrometers of copper, the total copper cross-section is 25 times 0.0216 square millimeters, or 0.54 square millimeters. In a 1.6 mm thick board, this array provides a thermal resistance of approximately 7.7 degrees Celsius per watt through the via copper alone.
Reducing the pitch to 0.7 mm would increase the via count to approximately 49 in the same pad area, reducing the array thermal resistance to approximately 3.9 degrees Celsius per watt. However, the reduced pitch creates narrower copper bridges between vias on the surface pad, which may not provide adequate solder joint area or may violate minimum copper-to-copper spacing rules for the fabrication process. In our standard capabilities, we maintain a minimum copper web of 0.15 mm between via holes on outer layers and 0.10 mm between anti-pads on inner layers. These constraints effectively establish the minimum via pitch for a given drill diameter.
The decision between fewer large vias and many small vias at the same total copper area generally favors smaller, more numerous vias for thermal applications. This is because smaller vias achieve higher plating uniformity, have shorter stub lengths when back-drilled, and distribute the heat more uniformly across the thermal pad area. However, smaller vias have higher aspect ratios for the same board thickness, which introduces the plating uniformity concerns discussed extensively in the context of HDI via reliability.
Via-in-Pad Technology for Thermal Applications
The most thermally efficient via array design places vias directly within the component solder pad rather than routing thermal relief traces from the pad to nearby vias. This via-in-pad approach eliminates the thermal resistance of the trace connections between the pad and the vias, and it maximizes the overlap between the heat source (the component die attach area) and the thermal conduction path (the via array). However, via-in-pad construction for solderable pads requires that the vias be filled and planarized to create a flat, solderable surface.
An unfilled via within a solder pad creates several problems during assembly. During reflow, molten solder wicks down into the via, reducing the solder volume available for the joint and potentially creating voids beneath the component. If the via is open on the bottom side, solder can wick completely through, creating solder balls on the bottom of the board that may cause shorts to bottom-side components. The reduced solder volume and voiding degrade both the electrical connection and the thermal interface between the component and the PCB.
The solution is via-in-pad filling and planarization, a multi-step process that fills the via with a material, closes the via openings, and planarizes the surface to a flatness suitable for solder paste printing. Several filling approaches are used in industry, each with distinct thermal and mechanical properties.
Conductive epoxy fill uses a silver or copper particle-filled polymer that is screened into the via holes from one side, cured, then surface-ground flat. The thermal conductivity of conductive epoxy fills ranges from 3 to 15 W/m-K depending on the filler loading, which is dramatically better than air but far below solid copper. The advantage of epoxy fill is process simplicity and cost effectiveness, making it suitable for applications where moderate thermal performance is acceptable.
Copper-filled vias use an electrolytic bottom-up plating process that completely fills the via with solid copper. This provides the maximum possible thermal conductivity through the via, essentially creating a solid copper thermal column. The process is significantly more expensive and time-consuming than epoxy fill, typically adding 30 to 50 percent to the bare board fabrication cost for the plating operation alone. However, for high-power applications where thermal resistance must be minimized, copper fill provides performance that no other method can match.
In our production facility, we offer both conductive epoxy fill and copper electrofill for via-in-pad applications. For most power electronics designs dissipating 5 to 15 watts per component, conductive epoxy fill with high-loading silver particles provides adequate thermal performance at reasonable cost. For designs with concentrated heat loads exceeding 20 watts per square centimeter, or for applications where the PCB thermal resistance directly limits device junction temperature margin, we recommend copper electrofill despite the cost premium.
Planarization and Surface Quality for Assembly
After via filling, the surface must be planarized to achieve the flatness required for reliable solder paste printing. The IPC standard for via-in-pad surface quality specifies that the filled via surface should be within plus or minus 0.05 mm of the surrounding pad copper, which is achievable with mechanical grinding followed by a final surface plating step that covers the fill material with a continuous copper layer.
This cap plating step is critical for two reasons. First, it provides a copper surface that is compatible with all standard surface finishes including ENIG, HASL, OSP, and immersion silver. Without the cap, the exposed fill material may not accept these finishes uniformly. Second, the cap creates a hermetic seal over the fill material, preventing flux penetration into the filled via during reflow that could cause outgassing and void formation at the solder interface.
From our assembly yield data, properly planarized and cap-plated via-in-pad structures achieve solder void rates comparable to solid copper pads, typically below 15 percent voiding by area on the thermal pad. Inadequately planarized vias, where dimpling or doming exceeds 0.05 mm, consistently produce higher void rates because the surface irregularity disrupts solder paste transfer during printing and creates nucleation sites for gas entrapment during reflow.
Thermal Resistance Calculation Methodology
For designers optimizing thermal via arrays, a systematic calculation methodology allows comparison of different array configurations against the thermal budget for the application. The overall thermal resistance from the component junction to the ambient environment can be decomposed into series elements: junction to case, case to solder, solder to PCB top surface, PCB through-thickness, PCB bottom surface to heatsink, and heatsink to ambient.
The PCB through-thickness component is where thermal via design has its influence. For a given array geometry, the effective thermal resistance can be calculated as follows. First, compute the total copper cross-sectional area of all vias in the array, considering whether the vias are hollow plated, epoxy filled, or copper filled. Second, compute the equivalent thermal conductivity of the composite via region by area-weighting the thermal conductivities of copper, fill material, and dielectric. Third, calculate the thermal resistance as the board thickness divided by the product of the composite thermal conductivity and the total array area.
For a practical example, consider a 25 mm squared thermal pad on a 1.6 mm board with 36 vias at 0.3 mm diameter copper-filled. The total copper area is 36 times pi times 0.15 squared, yielding 2.54 square millimeters. The FR4 area is 625 minus 2.54, yielding 622.46 square millimeters. The thermal resistance of the copper paths in parallel is 1.6 mm divided by 385 W/m-K times 2.54 square millimeters, giving approximately 1.6 degrees Celsius per watt. The FR4 parallel path contributes 1.6 divided by 0.3 times 622.46 in appropriate units, giving approximately 8.6 degrees Celsius per watt. The combined parallel resistance is approximately 1.35 degrees Celsius per watt for the copper-filled array compared to approximately 8.5 degrees Celsius per watt for the same board area without vias.
This six-fold reduction in PCB thermal resistance demonstrates why thermal via arrays are essential for power electronics applications. Without the via array, the PCB would contribute 8.5 degrees Celsius per watt to the thermal stack, which for a 10-watt device would mean 85 degrees Celsius of temperature rise across the board thickness alone, making adequate cooling impossible without active measures.
Interaction with Internal Copper Planes
Thermal via arrays necessarily pass through internal copper layers, which can serve as lateral heat spreaders that further reduce the effective thermal resistance. A solid copper plane connected to the thermal via array spreads heat laterally away from the via cluster, increasing the effective area available for convection or radiation from the board surfaces. This spreading effect is particularly significant for boards with large ground or power planes that provide uninterrupted copper across substantial areas.
However, the anti-pads required for vias that are not connected to a given plane layer interrupt the copper continuity and reduce the spreading effectiveness. For thermal vias that pass through signal reference planes without electrical connection, the anti-pad creates a void in the plane that limits lateral conduction. For this reason, many power electronics designs intentionally connect thermal vias to one or more internal power or ground planes, using these connections both for electrical current distribution and for thermal spreading.
In designs where the thermal via array connects to internal planes on multiple layers, the thermal model becomes more complex because heat flows both vertically through the via barrels and laterally through the plane connections. This three-dimensional heat flow generally improves thermal performance beyond what the simple one-dimensional via calculation predicts, but accurate modeling requires finite element analysis that accounts for the specific geometry of plane connections, anti-pads on non-connected layers, and the thermal boundary conditions on all board surfaces.
Our engineering team provides thermal simulation support for customers designing power electronics PCBs, using finite element models that incorporate the actual layer stackup, copper distribution, and via array geometry. These simulations predict the steady-state temperature distribution across the board and identify thermal bottlenecks that can be addressed through design modifications. The goal is to achieve a design where the PCB thermal contribution to the overall thermal stack is minimized to the extent that is economically justified, allowing the power devices to operate within their safe operating area with adequate temperature margin for the target product lifetime.
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