PCB Stackup & Impedance Control: Sourcing the Right Fab

Your USB 3.0 link drops to USB 2.0 speeds. Your Ethernet PHY throws CRC errors under load. Your DDR3 won't train at rated frequency. You've checked the firmware, swapped the crystal, reflowed the chip. The real culprit is often invisible on the schematic: the fab built your board with a stackup that destroyed your impedance, and a $2 cost-down on the PCB just cost you a respin.

If your design has any of USB, Ethernet, HDMI, MIPI, RF, or DDR, you have controlled-impedance traces — whether you specified them or not. The question is whether the fab knows it.

What controlled impedance actually depends on

Trace impedance isn't a property of the trace. It's a property of the trace and the dielectric stack underneath it. The single-ended or differential impedance is set by:

• Trace width and copper thickness
• Dielectric height between the signal layer and its reference plane
• Dielectric constant (Dk) of the laminate

Change any one and the impedance moves. A 90 Ω USB differential pair designed for a 0.1 mm prepreg becomes 100+ Ω if the fab uses 0.13 mm prepreg to fit their standard press. Nothing on your Gerbers looks wrong. The signal integrity is just gone.

2 vs 4 vs 6 layers — it's about reference planes

Layer count for high-speed design isn't about routing density. It's about giving every fast signal a clean, adjacent reference plane.

• 2 layers: no usable controlled impedance for anything fast. The reference is too far away and too noisy. Fine for power and slow GPIO, not for USB or Ethernet.
• 4 layers: the practical minimum for controlled impedance. A signal / GND / PWR / signal stack gives your outer-layer traces a solid ground reference. Most USB 2.0, 100 Mbit Ethernet, and basic MIPI designs live here.
• 6 layers: when you need multiple routing layers each with a dedicated adjacent plane — DDR3/4, USB 3.x, gigabit Ethernet, RF front ends. The extra planes let you keep return currents tight and crosstalk down.

Going from 4 to 6 layers on a small board adds roughly 30-50% to bare-board cost. On a respin caused by failed signal integrity, that's the cheapest insurance you'll ever buy.

Why a cheap fab ruins your impedance

A budget fab quotes against their standard stackup. They have a press configuration that's efficient for them, and unless you constrain it, they'll substitute prepreg thicknesses and laminate Dk to match it. They may also swap your specified laminate (say, a Dk-3.8 material) for a cheaper one with a different Dk. Your trace widths were calculated for the original stack; now they're wrong.

This is the same dynamic as PCB material substitution generally: the corner that gets cut is the one you didn't pin down in writing. Tg, Dk, copper weight, and stack height all move when a fab optimizes for cost over spec.

A concrete case: a 4-layer IoT gateway with a gigabit PHY shipped with random link-negotiation failures on about 8% of units. The fab had used a thicker core than the designer assumed, pushing the differential pairs from 100 Ω to roughly 115 Ω. The fix was free — just specifying the exact stackup — but it took a respin to find.

What to send the fab

Don't send Gerbers and hope. Send a stackup drawing and an impedance table, and require a report back:

1. Target impedances: e.g. USB D+/D-: 90 Ω differential, Ethernet pairs: 100 Ω differential, RF trace: 50 Ω single-ended.
2. Specified layer stackup: layer order, copper weights (e.g. 1 oz outer / 0.5 oz inner), and named laminate with its Dk/Tg — not "FR4," which means nothing precise.
3. A request for the fab's proposed stackup before production, so you can confirm their prepreg/core heights hit your impedance.
4. A request for the impedance test coupon report with each batch. Reputable fabs run a TDR coupon and will send the measured values.

If the fab can't produce an impedance report or pushes back on sharing their stackup, that's your answer about whether they can build the board.

This is hard to police from another continent. If you don't have an engineer who can read a stackup and compare it to the impedance report, an engineering-led agent like China Sourcing Agents will check the fab's proposed stack and TDR coupon against your spec during the audit — before the panel goes into the press, not after a respin.

Pin the stackup. Demand the impedance coupon. The board that meets spec on paper is the only one that meets it on the wire.