TL;DR
Part 2 of letting an AI agent (Codex, driving KiCad through its CLI) design my Raspberry Pi CM4 Mini-ITX IO board. The board is now fully routed and adopted as the official design: ERC 0, DRC 0, unrouted nets 0, schematic↔PCB mismatches 0. Vendor-model power simulations that timed out last time now complete all 12 cases. And yet the strict all-checks pass flag is still false, and I am not releasing Gerbers — because a fault simulation leaves about −1.35 V on a power controller pin, and nobody has explained it away yet.
This is a series: Part 1 — 486 checks and the first scoreboard.
The scoreboard: Part 1 → Part 2
| Check | Part 1 (Oct 24) | Part 2 (Oct 25) |
|---|---|---|
| ERC errors | 0 | 0 |
| DRC errors | 244 | 0 |
| Unrouted nets | 1,464 | 0 |
| Schematic↔PCB mismatches | 0 | 0 |
| Warnings | 188 | 124 (94 copper slivers, 21 vias, 9 track ends) |
| Board | placement stage, 0 tracks | 170×170 mm, 8 layers, 963 footprints, 18,500 tracks + vias |
| Vendor-model startup sims | timed out twice, undetermined | 12/12 cases completed to 300 ms |
| Strict all-checks pass | false | still false (warnings + one unresolved fault case) |
The formal re-verification ran on 2026-10-25 at 11:42 JST and also confirmed that none of the 52 input files changed while the checks were running — the loop checks its own homework, including whether the homework moved.
Top side. The silkscreen still says "ROUTED ENGINEERING PROTOTYPE / DO NOT FABRICATE" — that text has earned its place.
Bottom side, with the power stages and the back of the ATX connector.
What it took to finish routing
- High-speed differential sections were reworked segment by segment: length-error cancellation across the AC-coupling capacitors, layer usage, and via depth differences were corrected. On D5, both capacitors moved to the B side and the clock termination was repositioned. The loop also verified that no existing signal's reference GND plane gained new splits.
- Power monitor window adjusted: R119 went 150 Ω → 200 Ω and R272 9.31 kΩ → 9.42 kΩ, synced across schematic, PCB, BOM and part data. A pin type on U300.A8 was corrected to match the actual output.
- The verification scripts themselves got fixed: a stale dependency on old power summaries and an absolute/relative path mismatch in file collation. The checker now verifies that the board, the part data and the stored analysis results actually agree with each other.
Simulations: the static picture holds, the dynamic picture advanced
Re-run on the adopted board:
- 384 passive SPICE conditions across the 6 base power rails
- Voltage drop including 357 shared-GND points
- 68 control/sense paths, 16 power sections, 48 capacitor paths
- 32,768 PG/UV analysis conditions — the tightest power-good re-engagement margin across the 4 branches is about 5.345 mV
All of that holds within the declared static conditions. And the part that was stuck last time moved: with the original ADI/Nexperia vendor models, 4 power branches × (startup, output short circuit, normal input loss) = 12 cases, all numerically completed to 300 ms, passing limited terminal-voltage and MOSFET-voltage checks against the saved waveforms.
The catch: −1.35 V that nobody has explained away
A separate internal-fault diagnosis puts a 1 mΩ short on the upstream BUCK side. On the latest board, the saved waveforms still show:
| LTC4229 pin | Minimum in saved waveform |
|---|---|
| IN | ≈ −1.338 V |
| DSRC | ≈ −1.353 V |
The check floor is −0.3 V. Added-capacitor and snubber proposals did not fix it, so they were not adopted into the board. Two honest caveats cut in opposite directions: this is a partial model with assumed parasitics and supply response, so it does not prove the real board would be damaged — but "the model might be wrong" is not a passing grade either. Until this is resolved, the design does not get called complete, problem-free, or manufacturable, and the Gerber/drill/assembly outputs stay unreleased.
Still open after that: fault tolerance, the full power control loop, high-speed SI, thermal/EMI, simultaneous real-world I/O, and case/assembly/manufacturing checks.
Questions for you
- When a partial SPICE model shows a below-absolute-maximum pin voltage that layout tweaks won't move, where do you look first — the model's assumed parasitics, or the circuit?
- Would you fabricate a board whose own verification suite refuses to say "pass"?
Series: Part 1 covered the spec (DisplayPort + HDMI, 2× USB-A, 2× USB-C, a PCIe switch feeding 2 slots + 2 M.2, ATX 24-pin power) and the first 486 power-analysis conditions. The Japanese edition of Part 1 is on Qiita. Part 2 in Japanese is on Qiita too.
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