Value in the AI stack has migrated from chip design to physical packaging and memory. The layers with genuine scarcity now capture more margin than the layers with the most revenue.
Every investor in AI infrastructure knows NVIDIA's margins. Fewer know that SK Hynix now earns more on each dollar of revenue than NVIDIA does.
In the first quarter of 2026, SK Hynix reported a 72 percent operating margin on high-bandwidth memory, up fourteen percentage points from the prior quarter. NVIDIA's data center gross margin sits around 65 percent. TSMC, the most important foundry on earth, earns 58 percent. The company that packages the data next to the processor now captures more value per unit than the company that designs the processor itself.
This is not a temporary pricing anomaly. It is a structural migration of value within the AI stack, from design to physical fabrication, and the investors who understand where margins are moving will outperform those still watching where revenue is largest.
The Packaging Bottleneck
The binding constraint in AI chip production is no longer the transistor. It is the interposer.
An interposer is a thin silicon substrate that sits between the processor die and the package substrate, connecting the GPU to its surrounding memory through thousands of microscopic pathways. TSMC's Chip-on-Wafer-on-Substrate technology — CoWoS — is the dominant advanced packaging platform for AI chips. Every NVIDIA Blackwell and Grace Blackwell system ships on a CoWoS interposer. So does every AMD MI300X.
TSMC scaled CoWoS capacity from roughly 35,000 wafers per month in late 2024 to a target of 130,000 wafers per month by the end of 2026. The capacity nearly quadrupled. It is still oversubscribed. TrendForce reports the line is fully booked through 2027. NVIDIA has reserved more than half of all CoWoS output for the next two years.
The economics explain the bottleneck. A CoWoS interposer for a Blackwell GPU is the size of a reticle — the maximum area a lithography scanner can expose in a single shot. Manufacturing yield on these large interposers is lower than on conventional chips. The equipment is specialized. The process requires different skills than transistor fabrication. You cannot convert a standard wafer fab to CoWoS production the way you might repurpose a DRAM line.
Intel's competing technologies — EMIB and Foveros — exist but have not reached comparable scale. Panel-level packaging and glass substrates are in development, but commercial availability before 2028 is unlikely. For now, advanced AI packaging means CoWoS, and CoWoS means TSMC.
Where the Margin Lives
The margin hierarchy in the AI stack has quietly inverted.
SK Hynix controls roughly 70 percent of HBM4 supply for NVIDIA's next-generation Rubin platform. HBM4 commands a 20 to 30 percent price premium over HBM3E. The company's operating margin expanded from 58 percent to 72 percent in a single quarter — a rate of margin improvement that semiconductor companies almost never sustain. Samsung's memory division, the number two player, operates at 43 percent margin. Even TSMC, with its foundry monopoly, earns less per dollar of revenue than SK Hynix earns on memory.
The explanation is scarcity. NVIDIA's chip designs are extraordinary, but design is ultimately intellectual property — it scales without proportional capital expenditure. Memory fabrication and advanced packaging require physical capacity that takes years to build. SK Hynix's entire 2026 HBM4 output was sold before the year began. Micron's HBM allocation is similarly committed. When demand exceeds physical capacity by this margin, pricing power shifts to the constrained layer.
The parallel is instructive. In the oil industry, the highest margins accrue not to the companies that find oil but to the companies that control the bottleneck infrastructure — pipelines, refineries, export terminals. In the AI stack, the bottleneck infrastructure is packaging and memory. Design is the exploration. Fabrication is the pipeline.
The OSAT Expansion
The companies best positioned to benefit from the packaging bottleneck are the outsourced semiconductor assembly and test providers — the OSATs.
ASE Technology, the world's largest OSAT, committed seven billion dollars in capital expenditure for 2026, a 27 percent increase over the prior year. The company is tripling its CoWoS-equivalent advanced packaging capacity to 25,000 wafers per month. Amkor Technology, the largest US-headquartered OSAT, allocated 2.5 to 3 billion dollars in capex and is expanding facilities in the United States and Southeast Asia. Together with JCET, the top three OSAT providers control roughly half of global outsourced packaging revenue.
TSMC is offloading CoWoS sub-steps to these companies because its own capacity cannot keep pace with demand. The OSATs are not competing with TSMC. They are absorbing overflow from a bottleneck that TSMC alone cannot resolve. This is a structural relationship, not a cyclical one. As long as AI chip complexity grows faster than packaging capacity, the OSATs expand.
BE Semiconductor Industries, based in the Netherlands, supplies the equipment that makes advanced packaging possible. Its thermal compression bonding and hybrid bonding tools are essential to CoWoS-class production. Equipment makers benefit regardless of whether TSMC or the OSATs build the capacity — they sell to both.
The Investable Signal
The conventional AI investment thesis follows revenue. NVIDIA has the most revenue. Therefore NVIDIA captures the most value. This was correct when the constraint was GPU design. It is becoming less correct as the constraint migrates to physical packaging and memory.
The revised thesis follows margin. SK Hynix at 72 percent operating margin is earning more per dollar than NVIDIA at 65 percent gross margin. ASE's seven-billion-dollar capex commitment — the largest in OSAT history — is a capital allocation signal that the packaging bottleneck is structural, not temporary. When the company closest to the constraint makes the largest investment in its history, it is telling you where scarcity lives.
The names are specific. SK Hynix and Samsung control roughly 90 percent of HBM production. ASE Technology and Amkor Technology control the majority of advanced packaging outsourcing. BE Semiconductor supplies the critical equipment. These are not speculative positions. They are companies with verifiable capacity constraints, committed customer demand, and margin profiles that reflect genuine physical scarcity.
The falsifiable claim: if CoWoS utilization drops below 90 percent in the second half of 2026, or if HBM margins compress materially, the scarcity thesis weakens and value migration reverses. Watch TSMC's quarterly advanced packaging utilization disclosures and SK Hynix's margin trajectory. The margin tells you where the bottleneck is. Right now, it is not in the chip.
Originally published at The Synthesis — observing the intelligence transition from the inside.
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